From 3f5b60856a004d97bac702fb6c8ff2490f851bdd Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Fri, 28 Jun 2019 13:49:04 -0700 Subject: [PATCH] Fixed key error with analytical delay of write ports. --- compiler/sram/sram_base.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 547bc222..ff41e9f2 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -529,6 +529,7 @@ class sram_base(design, verilog, lef): elif port in self.readwrite_ports: control_logic = self.control_logic_rw else: + delays[port] = self.return_delay(0,0) #Write ports do not have a lib defined delay, marked as 0 continue clk_to_wlen_delays = control_logic.analytical_delay(corner, slew, load) wlen_to_dout_delays = self.bank.analytical_delay(corner,slew,load,port) #port should probably be specified...