mirror of https://github.com/VLSIDA/OpenRAM.git
Update column decoder and dff array supplies
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parent
c8905c410a
commit
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@ -87,8 +87,8 @@ class column_decoder(design.design):
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def route_supplies(self):
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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""" Propagate all vdd/gnd pins up to this level for all modules """
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if self.col_addr_size == 1:
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if self.col_addr_size == 1:
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self.copy_power_pins(self.column_decoder_inst, "vdd")
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self.copy_layout_pin(self.column_decoder_inst, "vdd")
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self.copy_power_pins(self.column_decoder_inst, "gnd")
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self.copy_layout_pin(self.column_decoder_inst, "gnd")
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else:
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else:
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self.route_vertical_pins("vdd", self.insts, xside="rx",)
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self.route_vertical_pins("vdd", self.insts, xside="rx",)
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self.route_vertical_pins("gnd", self.insts, xside="lx",)
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self.route_vertical_pins("gnd", self.insts, xside="lx",)
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@ -108,22 +108,23 @@ class dff_array(design.design):
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return dout_name
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return dout_name
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def route_supplies(self):
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def route_supplies(self):
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if OPTS.experimental_power and self.rows > 1:
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if self.rows > 1:
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# Vertical straps on ends if multiple rows
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# Vertical straps on ends if multiple rows
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left_dff_insts = [self.dff_insts[x, 0] for x in range(self.rows)]
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left_dff_insts = [self.dff_insts[x, 0] for x in range(self.rows)]
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right_dff_insts = [self.dff_insts[x, self.columns-1] for x in range(self.rows)]
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right_dff_insts = [self.dff_insts[x, self.columns-1] for x in range(self.rows)]
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self.route_vertical_pins("vdd", left_dff_insts, xside="lx", yside="cy")
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self.route_vertical_pins("vdd", left_dff_insts, xside="lx", yside="cy")
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self.route_vertical_pins("gnd", right_dff_insts, xside="rx", yside="cy")
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self.route_vertical_pins("gnd", right_dff_insts, xside="rx", yside="cy")
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else:
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else:
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for row in range(self.rows):
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for col in range(self.columns):
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# Continous vdd rail along with label.
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vdd_pin=self.dff_insts[row, col].get_pin("vdd")
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self.copy_power_pin(vdd_pin)
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# Continous gnd rail along with label.
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# Add connections every 4 cells
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gnd_pin=self.dff_insts[row, col].get_pin("gnd")
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for col in range(1, self.columns, 4):
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self.copy_power_pin(gnd_pin)
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vdd_pin=self.dff_insts[0, col].get_pin("vdd")
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self.add_power_pin("vdd", vdd_pin.lc())
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# Add connections every 4 cells
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for col in range(1, self.columns, 4):
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gnd_pin=self.dff_insts[0, col].get_pin("gnd")
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self.add_power_pin("gnd", gnd_pin.rc())
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def add_layout_pins(self):
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def add_layout_pins(self):
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for row in range(self.rows):
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for row in range(self.rows):
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