From 3e02a0e7dff2f2b06fc0703e48b7299d31ec3796 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 17 May 2022 15:49:50 -0700 Subject: [PATCH] Update column decoder and dff array supplies --- compiler/modules/column_decoder.py | 4 ++-- compiler/modules/dff_array.py | 19 ++++++++++--------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/compiler/modules/column_decoder.py b/compiler/modules/column_decoder.py index 9cb08284..f94786a2 100644 --- a/compiler/modules/column_decoder.py +++ b/compiler/modules/column_decoder.py @@ -87,8 +87,8 @@ class column_decoder(design.design): def route_supplies(self): """ Propagate all vdd/gnd pins up to this level for all modules """ if self.col_addr_size == 1: - self.copy_power_pins(self.column_decoder_inst, "vdd") - self.copy_power_pins(self.column_decoder_inst, "gnd") + self.copy_layout_pin(self.column_decoder_inst, "vdd") + self.copy_layout_pin(self.column_decoder_inst, "gnd") else: self.route_vertical_pins("vdd", self.insts, xside="rx",) self.route_vertical_pins("gnd", self.insts, xside="lx",) diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 99b59064..226db997 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -108,22 +108,23 @@ class dff_array(design.design): return dout_name def route_supplies(self): - if OPTS.experimental_power and self.rows > 1: + if self.rows > 1: # Vertical straps on ends if multiple rows left_dff_insts = [self.dff_insts[x, 0] for x in range(self.rows)] right_dff_insts = [self.dff_insts[x, self.columns-1] for x in range(self.rows)] self.route_vertical_pins("vdd", left_dff_insts, xside="lx", yside="cy") self.route_vertical_pins("gnd", right_dff_insts, xside="rx", yside="cy") else: - for row in range(self.rows): - for col in range(self.columns): - # Continous vdd rail along with label. - vdd_pin=self.dff_insts[row, col].get_pin("vdd") - self.copy_power_pin(vdd_pin) - # Continous gnd rail along with label. - gnd_pin=self.dff_insts[row, col].get_pin("gnd") - self.copy_power_pin(gnd_pin) + # Add connections every 4 cells + for col in range(1, self.columns, 4): + vdd_pin=self.dff_insts[0, col].get_pin("vdd") + self.add_power_pin("vdd", vdd_pin.lc()) + + # Add connections every 4 cells + for col in range(1, self.columns, 4): + gnd_pin=self.dff_insts[0, col].get_pin("gnd") + self.add_power_pin("gnd", gnd_pin.rc()) def add_layout_pins(self): for row in range(self.rows):