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progress with rba pin mismatch

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jcirimel
2020-09-23 08:37:32 -07:00
parent 17e6e5eb16
commit 3dd72cdeac
4 changed files with 43 additions and 15 deletions
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compiler/modules/replica_bitcell_array.py
+4 -1
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@@ -294,7 +294,10 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
supplies = ["vdd", "gnd"]
# Used for names/dimensions only
self.cell = factory.create(module_type="bitcell")
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
self.cell = factory.create(module_type="bitcell")
else:
self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
# Main array
self.bitcell_array_inst=self.add_inst(name="bitcell_array",