diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index 4db81f46..d3c25ba0 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -294,7 +294,10 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
         supplies = ["vdd", "gnd"]
 
         # Used for names/dimensions only
-        self.cell = factory.create(module_type="bitcell")
+        if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
+            self.cell = factory.create(module_type="bitcell")
+        else:
+            self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
 
         # Main array
         self.bitcell_array_inst=self.add_inst(name="bitcell_array",
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index cbea26ce..a28aebf9 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -57,7 +57,6 @@ class replica_column(design.design):
         self.DRC_LVS()
 
     def add_pins(self):
-
         self.bitline_names = [[] for port in self.all_ports]
         col = 0
         for port in self.all_ports:
@@ -66,17 +65,29 @@ class replica_column(design.design):
         self.all_bitline_names = [x for sl in self.bitline_names for x in sl]
         self.add_pin_list(self.all_bitline_names, "OUTPUT")
 
-        self.wordline_names = [[] for port in self.all_ports]
-        for row in range(self.total_size):
-            for port in self.all_ports:
-                if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
-                    self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
-                else:
-                    self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
-                    self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
-        self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
-        self.add_pin_list(self.all_wordline_names, "INPUT")
+        if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
+            self.wordline_names = [[] for port in self.all_ports]
+            for row in range(self.total_size):
+                for port in self.all_ports:
+                    if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
+                        self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
+                    else:
+                        self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
+                        self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
+            self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
+            self.add_pin_list(self.all_wordline_names, "INPUT")
+        else:
+            self.wordline_names = [[] for port in self.all_ports]
+            for row in range(self.rows):
+                for port in self.all_ports:
+                    if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
+                        self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
+                    else:
+                        self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
+                        self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
 
+            self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
+            self.add_pin_list(self.all_wordline_names, "INPUT")
         self.add_pin("vdd", "POWER")
         self.add_pin("gnd", "GROUND")
 
diff --git a/compiler/tests/sram_1b_16_1rw_sky130.log b/compiler/tests/sram_1b_16_1rw_sky130.log
index 506212d1..f7fb9395 100644
--- a/compiler/tests/sram_1b_16_1rw_sky130.log
+++ b/compiler/tests/sram_1b_16_1rw_sky130.log
@@ -1,4 +1,9 @@
-WARNING: file magic.py: line 210: DRC Errors bitcell_array	9424
-
-ERROR: file magic.py: line 285: bitcell_array	LVS mismatch (results in /home/jesse/output/bitcell_array.lvs.report)
+ERROR: file hierarchy_spice.py: line 176: Connection mismatch:
+Inst (4) -> Mod (6)
+bl_0_0 -> bl0
+br_0_0 -> bl1
+vdd -> wl0
+gnd -> wl1
+ -> vpwr
+ -> vgnd
 
diff --git a/sram_1b_16_1rw_sky130.log b/sram_1b_16_1rw_sky130.log
index bd642b1d..18538d57 100644
--- a/sram_1b_16_1rw_sky130.log
+++ b/sram_1b_16_1rw_sky130.log
@@ -15,3 +15,12 @@
 [bitcell_base_array/__init__]: Creating replica_bitcell_array 4 x 4
 [replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4
 [bitcell_base_array/__init__]: Creating bitcell_array 4 x 4
+ERROR: file hierarchy_spice.py: line 176: Connection mismatch:
+Inst (4) -> Mod (6)
+bl_0_0 -> bl0
+br_0_0 -> bl1
+vdd -> wl0
+gnd -> wl1
+ -> vpwr
+ -> vgnd
+