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OpenRAM
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Merge branch 'dev' into s8_single_port

This commit is contained in:
jcirimel 2020-11-05 03:07:43 -08:00
parent e1d7d9dff7 9a38f7a5f4
commit 3dd5bd5675
134 changed files with 285 additions and 244 deletions
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15
compiler/base/custom_cell_properties.py
View File

@ -137,6 +137,21 @@ class cell_properties():
"""
def __init__(self):
self.names = {}
self.names["bitcell"] = "cell_6t"
self.names["bitcell_1rw_1r"] = "cell_1rw_1r"
self.names["bitcell_1w_1r"] = "cell_1w_1r"
self.names["dummy_bitcell"] = "dummy_cell_6t"
self.names["dummy_bitcell_1rw_1r"] = "dummy_cell_1rw_1r"
self.names["dummy_bitcell_1w_1r"] = "dummy_cell_1w_1r"
self.names["replica_bitcell"] = "replica_cell_6t"
self.names["replica_bitcell_1rw_1r"] = "replica_cell_1rw_1r"
self.names["replica_bitcell_1w_1r"] = "replica_cell_1w_1r"
self.names["col_cap_bitcell_6t"] = "col_cap_cell_6t"
self.names["col_cap_bitcell_1rw_1r"] = "col_cap_cell_1rw_1r"
self.names["col_cap_bitcell_1w_1r"] = "col_cap_cell_1w_1r"
self.names["row_cap_bitcell_6t"] = "row_cap_cell_6t"
self.names["row_cap_bitcell_1rw_1r"] = "row_cap_cell_1rw_1r"
self.names["row_cap_bitcell_1w_1r"] = "row_cap_cell_1w_1r"
self._bitcell = _bitcell._default()

7
compiler/bitcells/bitcell.py
View File

@ -7,7 +7,6 @@
#
import debug
from tech import cell_properties as props
from globals import OPTS
import bitcell_base
@ -27,10 +26,8 @@ class bitcell(bitcell_base.bitcell_base):
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar']
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.bitcell_name
super().__init__(name, cell_name)
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create bitcell")
self.nets_match = self.do_nets_exist(self.storage_nets)

7
compiler/bitcells/bitcell_1rw_1r.py
View File

@ -8,7 +8,6 @@
import debug
from tech import cell_properties as props
import bitcell_base
from globals import OPTS
class bitcell_1rw_1r(bitcell_base.bitcell_base):
@ -31,10 +30,8 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base):
"INPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar']
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.bitcell_name
super().__init__(name, cell_name)
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create bitcell with 1RW and 1R Port")
self.nets_match = self.do_nets_exist(self.storage_nets)

7
compiler/bitcells/bitcell_1w_1r.py
View File

@ -8,7 +8,6 @@
import debug
from tech import cell_properties as props
import bitcell_base
from globals import OPTS
class bitcell_1w_1r(bitcell_base.bitcell_base):
@ -31,10 +30,8 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
"INPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar']
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.bitcell_name
super().__init__(name, cell_name)
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create bitcell with 1W and 1R Port")
self.nets_match = self.do_nets_exist(self.storage_nets)

8
compiler/bitcells/bitcell_base.py
View File

@ -20,15 +20,15 @@ class bitcell_base(design.design):
"""
cell_size_layer = "boundary"
def __init__(self, name, cell_name, hard_cell=True):
design.design.__init__(self, name, cell_name)
def __init__(self, name, hard_cell=True):
design.design.__init__(self, name)
if hard_cell:
(self.width, self.height) = utils.get_libcell_size(cell_name,
(self.width, self.height) = utils.get_libcell_size(self.cell_name,
GDS["unit"],
layer[self.cell_size_layer])
self.pin_map = utils.get_libcell_pins(self.pin_names,
cell_name,
self.cell_name,
GDS["unit"])
self.add_pin_types(self.type_list)

10
compiler/bitcells/col_cap_bitcell_1rw_1r.py
View File

@ -12,7 +12,8 @@ import bitcell_base
class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
"""
todo"""
Column end cap cell.
"""
pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
props.bitcell.cell_1rw1r.pin.br0,
@ -22,11 +23,8 @@ class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
"POWER", "GROUND"]
def __init__(self, name="col_cap_cell_1rw_1r", cell_name=None):
if not cell_name:
cell_name = name
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, name, cell_name)
def __init__(self, name="col_cap_cell_1rw_1r"):
bitcell_base.bitcell_base.__init__(self, name)
debug.info(2, "Create col_cap bitcell 1rw+1r object")
self.no_instances = True

7
compiler/bitcells/dummy_bitcell.py
View File

@ -8,7 +8,6 @@
import debug
from tech import cell_properties as props
import bitcell_base
from globals import OPTS
class dummy_bitcell(bitcell_base.bitcell_base):
@ -25,10 +24,8 @@ class dummy_bitcell(bitcell_base.bitcell_base):
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.dummy_bitcell_name
super().__init__(name, cell_name)
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create dummy bitcell")

7
compiler/bitcells/dummy_bitcell_1rw_1r.py
View File

@ -8,7 +8,6 @@
import debug
from tech import cell_properties as props
import bitcell_base
from globals import OPTS
class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
@ -29,10 +28,8 @@ class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
"INPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.dummy_bitcell_name
super().__init__(name, cell_name)
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create dummy bitcell 1rw+1r object")

7
compiler/bitcells/dummy_bitcell_1w_1r.py
View File

@ -8,7 +8,6 @@
import debug
from tech import cell_properties as props
import bitcell_base
from globals import OPTS
class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
@ -29,10 +28,8 @@ class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
"INPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.dummy_bitcell_name
super().__init__(name, cell_name)
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create dummy bitcell 1w+1r object")

4
compiler/bitcells/dummy_pbitcell.py
View File

@ -18,14 +18,12 @@ class dummy_pbitcell(design.design):
"""
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = name
self.num_rw_ports = OPTS.num_rw_ports
self.num_w_ports = OPTS.num_w_ports
self.num_r_ports = OPTS.num_r_ports
self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
design.design.__init__(self, name, cell_name)
design.design.__init__(self, name)
debug.info(1, "create a dummy bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
self.num_w_ports,
self.num_r_ports))

6
compiler/bitcells/pbitcell.py
View File

@ -21,9 +21,7 @@ class pbitcell(bitcell_base.bitcell_base):
with a variable number of read/write, write, and read ports
"""
def __init__(self, name, cell_name=None, replica_bitcell=False, dummy_bitcell=False):
if not cell_name:
cell_name = name
def __init__(self, name, replica_bitcell=False, dummy_bitcell=False):
self.num_rw_ports = OPTS.num_rw_ports
self.num_w_ports = OPTS.num_w_ports
self.num_r_ports = OPTS.num_r_ports
@ -32,7 +30,7 @@ class pbitcell(bitcell_base.bitcell_base):
self.replica_bitcell = replica_bitcell
self.dummy_bitcell = dummy_bitcell
bitcell_base.bitcell_base.__init__(self, name, cell_name, hard_cell=False)
bitcell_base.bitcell_base.__init__(self, name, hard_cell=False)
fmt_str = "{0} rw ports, {1} w ports and {2} r ports"
info_string = fmt_str.format(self.num_rw_ports,
self.num_w_ports,

14
compiler/bitcells/replica_bitcell.py
View File

@ -6,11 +6,10 @@
# All rights reserved.
#
import debug
import utils
import bitcell_base
from tech import GDS, layer
from tech import cell_properties as props
from globals import OPTS
from tech import parameter, drc
import logical_effort
class replica_bitcell(bitcell_base.bitcell_base):
@ -27,11 +26,8 @@ class replica_bitcell(bitcell_base.bitcell_base):
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.replica_bitcell_name
# Ignore the name argument
super().__init__(name, cell_name)
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create replica bitcell object")
def get_stage_effort(self, load):
@ -52,7 +48,7 @@ class replica_bitcell(bitcell_base.bitcell_base):
"""Bitcell power in nW. Only characterizes leakage."""
from tech import spice
leakage = spice["bitcell_leakage"]
dynamic = 0 #temporary
dynamic = 0 # FIXME
total_power = self.return_power(dynamic, leakage)
return total_power

9
compiler/bitcells/replica_bitcell_1rw_1r.py
View File

@ -8,7 +8,8 @@
import debug
import bitcell_base
from tech import cell_properties as props
from globals import OPTS
from tech import parameter, drc
import logical_effort
class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
@ -28,10 +29,8 @@ class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.replica_bitcell_name
super().__init__(name, cell_name)
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create replica bitcell 1rw+1r object")
def get_stage_effort(self, load):

12
compiler/bitcells/replica_bitcell_1w_1r.py
View File

@ -8,9 +8,8 @@
import debug
import bitcell_base
from tech import cell_properties as props
from globals import OPTS
from tech import GDS, layer
import utils
from tech import parameter, drc
import logical_effort
class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
@ -30,13 +29,10 @@ class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
props.bitcell.cell_1w1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.replica_bitcell_name
super().__init__(name, cell_name)
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create replica bitcell 1w+1r object")
def get_stage_effort(self, load):
parasitic_delay = 1
size = 0.5 # This accounts for bitline being drained thought the access TX and internal node

12
compiler/bitcells/row_cap_bitcell_1rw_1r.py
View File

@ -12,20 +12,16 @@ import bitcell_base
class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
"""
A single bit cell which is forced to store a 0.
This module implements the single memory cell used in the design. It
is a hand-made cell, so the layout and netlist should be available in
the technology library. """
Row end cap cell.
"""
pin_names = [props.bitcell.cell_1rw1r.pin.wl0,
props.bitcell.cell_1rw1r.pin.wl1,
props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["INPUT", "INPUT", "GROUND"]
def __init__(self, name="row_cap_cell_1rw_1r", cell_name=None):
if not cell_name:
cell_name = name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
def __init__(self, name="row_cap_cell_1rw_1r"):
bitcell_base.bitcell_base.__init__(self, name)
debug.info(2, "Create row_cap bitcell 1rw+1r object")
self.no_instances = True

6
compiler/debug.py
View File

@ -26,9 +26,6 @@ def check(check, str):
log("ERROR: file {0}: line {1}: {2}\n".format(
os.path.basename(filename), line_number, str))
if globals.OPTS.debug_level > 0:
import pdb
pdb.set_trace()
assert 0
@ -40,9 +37,6 @@ def error(str, return_value=0):
log("ERROR: file {0}: line {1}: {2}\n".format(
os.path.basename(filename), line_number, str))
if globals.OPTS.debug_level > 0 and return_value != 0:
import pdb
pdb.set_trace()
assert return_value == 0

0
compiler/example_configs/riscv-scn4m_subm-16kbyte.py → compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py
View File

0
compiler/example_configs/riscv-scn4m_subm-1kbyte.py → compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py
View File

0
compiler/example_configs/riscv-scn4m_subm-2kbyte.py → compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py
View File

0
compiler/example_configs/riscv-scn4m_subm-4kbyte.py → compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py
View File

0
compiler/example_configs/riscv-scn4m_subm-8kbyte.py → compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py
View File

26
compiler/example_configs/riscv-sky130-1kbyte-1rw.py Normal file
View File

@ -0,0 +1,26 @@
word_size = 32
num_words = 256
write_size = 8
local_array_size = 16
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
tech_name = "sky130"
nominal_corner_only = True
route_supplies = False
check_lvsdrc = True
perimeter_pins = False
#netlist_only = True
#analytical_delay = False
output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name)
output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name)

4
compiler/example_configs/riscv-sky130-1kbyte.py → compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py
View File

@ -11,9 +11,9 @@ num_w_ports = 0
tech_name = "sky130"
nominal_corner_only = True
route_supplies = True
route_supplies = False
check_lvsdrc = True
perimeter_pins = True
perimeter_pins = False
#netlist_only = True
#analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,

26
compiler/example_configs/riscv-sky130-2kbyte-1rw.py Normal file
View File

@ -0,0 +1,26 @@
word_size = 32
num_words = 512
write_size = 8
local_array_size = 16
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
tech_name = "sky130"
nominal_corner_only = True
route_supplies = False
check_lvsdrc = True
perimeter_pins = False
#netlist_only = True
#analytical_delay = False
output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name)
output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name)

4
compiler/example_configs/riscv-sky130-2kbyte.py → compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py
View File

@ -11,9 +11,9 @@ num_w_ports = 0
tech_name = "sky130"
nominal_corner_only = True
route_supplies = True
route_supplies = False
check_lvsdrc = True
perimeter_pins = True
perimeter_pins = False
#netlist_only = True
#analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,

26
compiler/example_configs/riscv-sky130-4kbyte-1rw.py Normal file
View File

@ -0,0 +1,26 @@
word_size = 32
num_words = 1024
write_size = 8
local_array_size = 16
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
tech_name = "sky130"
nominal_corner_only = True
route_supplies = False
check_lvsdrc = True
perimeter_pins = False
#netlist_only = True
#analytical_delay = False
output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name)
output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name)

4
compiler/example_configs/riscv-sky130-4kbyte.py → compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py
View File

@ -11,9 +11,9 @@ num_w_ports = 0
tech_name = "sky130"
nominal_corner_only = True
route_supplies = True
route_supplies = False
check_lvsdrc = True
perimeter_pins = True
perimeter_pins = False
#netlist_only = True
#analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,

25
compiler/globals.py
View File

@ -208,11 +208,9 @@ def setup_bitcell():
# If we have non-1rw ports,
# and the user didn't over-ride the bitcell manually,
# figure out the right bitcell to use
if (OPTS.bitcell == "bitcell"):
if OPTS.bitcell == "bitcell":
if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0):
OPTS.bitcell = "bitcell"
OPTS.bitcell_name = "cell_6t"
else:
ports = ""
if OPTS.num_rw_ports > 0:
@ -225,20 +223,13 @@ def setup_bitcell():
if ports != "":
OPTS.bitcell_suffix = "_" + ports
OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix
OPTS.bitcell_name = "cell" + OPTS.bitcell_suffix
OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell
OPTS.dummy_bitcell_name = "dummy_" + OPTS.bitcell_name
OPTS.replica_bitcell = "replica_" + OPTS.bitcell
OPTS.replica_bitcell_name = "replica_" + OPTS.bitcell_name
elif (OPTS.bitcell == "pbitcell"):
elif OPTS.bitcell == "pbitcell":
OPTS.bitcell = "pbitcell"
OPTS.bitcell_name = "pbitcell"
OPTS.dummy_bitcell = "dummy_pbitcell"
OPTS.dummy_bitcell_name = "dummy_pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.replica_bitcell_name = "replica_pbitcell"
# See if bitcell exists
try:
@ -248,11 +239,8 @@ def setup_bitcell():
# or its custom replica bitcell
# Use the pbitcell (and give a warning if not in unit test mode)
OPTS.bitcell = "pbitcell"
OPTS.bitcell_name = "pbitcell"
OPTS.dummy_bitcell = "dummy_pbitcell"
OPTS.dummy_bitcell_name = "dummy_pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.replica_bitcell_name = "replica_pbitcell"
if not OPTS.is_unit_test:
debug.warning("Using the parameterized bitcell which may have suboptimal density.")
debug.info(1, "Using bitcell: {}".format(OPTS.bitcell))
@ -269,8 +257,8 @@ def get_tool(tool_type, preferences, default_name=None):
if default_name:
exe_name = find_exe(default_name)
if exe_name == None:
debug.error("{0} not found. Cannot find {1} tool.".format(default_name,
tool_type),
debug.error("{0} not found. Cannot find {1} tool.".format(default_name, tool_type)
+ "Disable DRC/LVS with check_lvsdrc=False to ignore.",
2)
else:
debug.info(1, "Using {0}: {1}".format(tool_type, exe_name))
@ -283,8 +271,7 @@ def get_tool(tool_type, preferences, default_name=None):
return(name, exe_name)
else:
debug.info(1,
"Could not find {0}, trying next {1} tool.".format(name,
tool_type))
"Could not find {0}, trying next {1} tool.".format(name, tool_type))
else:
return(None, "")
@ -619,4 +606,4 @@ def report_status():
if OPTS.trim_netlist:
debug.print_raw("Trimming netlist to speed up characterization (trim_netlist=False to disable).")
if OPTS.nominal_corner_only:
debug.print_raw("Only characterizing nominal corner.")
debug.print_raw("Only generating nominal corner timing.")

2
compiler/sram/sram_config.py
View File

@ -39,7 +39,7 @@ class sram_config:
def compute_sizes(self):
""" Computes the organization of the memory using bitcell size by trying to make it square."""
bitcell = factory.create(module_type=OPTS.bitcell, cell_name=OPTS.bitcell_name)
bitcell = factory.create(module_type=OPTS.bitcell)
debug.check(self.num_banks in [1, 2, 4],
"Valid number of banks are 1 , 2 and 4.")

1
compiler/tests/04_and2_dec_test.py
View File

@ -15,6 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class and2_dec_test(openram_test):
def runTest(self):

1
compiler/tests/04_pinv_dec_1x_test.py
View File

@ -15,6 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class pinv_dec_1x_test(openram_test):
def runTest(self):

1
compiler/tests/05_bitcell_array_1rw_1r_test.py
View File

@ -15,7 +15,6 @@ from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
class bitcell_array_1rw_1r_test(openram_test):

1
compiler/tests/06_hierarchical_decoder_pbitcell_test.py
View File

@ -15,6 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class hierarchical_decoder_pbitcell_test(openram_test):
def runTest(self):

1
compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
View File

@ -15,6 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class hierarchical_predecode2x4_pbitcell_test(openram_test):
def runTest(self):

1
compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
View File

@ -15,6 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class hierarchical_predecode3x8_pbitcell_test(openram_test):
def runTest(self):

1
compiler/tests/06_hierarchical_predecode4x16_test.py
View File

@ -16,7 +16,6 @@ from sram_factory import factory
import debug
# @unittest.skip("SKIPPING hierarchical_predecode4x16_test")
class hierarchical_predecode4x16_test(openram_test):
def runTest(self):

1
compiler/tests/08_precharge_array_1rw_1r_test.py
View File

@ -15,6 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class precharge_1rw_1r_test(openram_test):
def runTest(self):

1
compiler/tests/09_sense_amp_array_1rw_1r_test.py
View File

@ -15,6 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class sense_amp_test(openram_test):
def runTest(self):

1
compiler/tests/10_write_driver_array_1rw_1r_test.py
View File

@ -15,6 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class write_driver_test(openram_test):
def runTest(self):

1
compiler/tests/10_write_mask_and_array_1rw_1r_test.py
View File

@ -9,7 +9,6 @@
import unittest
from testutils import *
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS

2
compiler/tests/12_tri_gate_array_test.py
View File

@ -15,6 +15,8 @@ from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 12_tri_gate_array_test")
class tri_gate_array_test(openram_test):
def runTest(self):

1
compiler/tests/14_replica_bitcell_array_1rw_1r_test.py
View File

@ -13,6 +13,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class replica_bitcell_array_1rw_1r_test(openram_test):
def runTest(self):

1
compiler/tests/14_replica_column_1rw_1r_test.py
View File

@ -13,6 +13,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class replica_column_test(openram_test):
def runTest(self):

2
compiler/tests/14_replica_column_test.py
View File

@ -25,12 +25,10 @@ class replica_column_test(openram_test):
self.local_check(a)
debug.info(2, "Testing replica column for cell_1rw_1r")
globals.setup_bitcell()
a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
self.local_check(a)
debug.info(2, "Testing replica column for cell_1rw_1r")
globals.setup_bitcell()
a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2)
self.local_check(a)

1
compiler/tests/18_port_data_wmask_1rw_1r_test.py
View File

@ -7,7 +7,6 @@
import unittest
from testutils import *
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS

1
compiler/tests/19_single_bank_wmask_1rw_1r_test.py
View File

@ -15,6 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class single_bank_wmask_1rw_1r_test(openram_test):
def runTest(self):

1
compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
View File

@ -16,7 +16,6 @@ from sram_factory import factory
import debug
# @unittest.skip("SKIPPING psram_1bank_2mux_1rw_1w_wmask_test, multiport layout not complete")
class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
def runTest(self):

1
compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py
View File

@ -16,7 +16,6 @@ from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test")
class psram_1bank_nomux_func_test(openram_test):
def runTest(self):

2
compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py
View File

@ -9,7 +9,6 @@
import unittest
from testutils import *
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
@ -17,7 +16,6 @@ from sram_factory import factory
import debug
# @unittest.skip("SKIPPING sram_wmask_1w_1r_func_test")
class sram_wmask_1w_1r_func_test(openram_test):
def runTest(self):

10
compiler/verify/__init__.py
View File

@ -15,7 +15,6 @@ run_pex, repsectively. If there is an error, they should abort and report the er
If not, OpenRAM will continue as if nothing happened!
"""
import os
import debug
from globals import OPTS
from globals import get_tool
@ -49,7 +48,8 @@ elif "assura"==OPTS.drc_exe[0]:
elif "magic"==OPTS.drc_exe[0]:
from .magic import run_drc, print_drc_stats
else:
debug.warning("Did not find a supported DRC tool.")
debug.error("Did not find a supported DRC tool."
+ "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2)
if not OPTS.lvs_exe:
from .none import run_lvs, print_lvs_stats
@ -60,7 +60,8 @@ elif "assura"==OPTS.lvs_exe[0]:
elif "netgen"==OPTS.lvs_exe[0]:
from .magic import run_lvs, print_lvs_stats
else:
debug.warning("Did not find a supported LVS tool.")
debug.warning("Did not find a supported LVS tool."
+ "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2)
if not OPTS.pex_exe:
@ -70,7 +71,8 @@ elif "calibre"==OPTS.pex_exe[0]:
elif "magic"==OPTS.pex_exe[0]:
from .magic import run_pex,print_pex_stats
else:
debug.warning("Did not find a supported PEX tool.")
debug.warning("Did not find a supported PEX tool."
+ "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2)
if OPTS.tech_name == "sky130":
if OPTS.magic_exe and "magic"==OPTS.magic_exe[0]:

3
compiler/verify/magic.py
View File

@ -77,8 +77,7 @@ def write_magic_script(cell_name, extract=False, final_verification=False):
f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1]))
f.write("gds polygon subcell true\n")
f.write("gds warning default\n")
# This causes substrate contacts to not be extracted
f.write("# gds readonly true\n")
f.write("gds readonly true\n")
f.write("gds read {}.gds\n".format(cell_name))
f.write("load {}\n".format(cell_name))
# Flatten the cell to get rid of DRCs spanning multiple layers