diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index fc2445ab..c592665a 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -137,6 +137,21 @@ class cell_properties(): """ def __init__(self): self.names = {} + self.names["bitcell"] = "cell_6t" + self.names["bitcell_1rw_1r"] = "cell_1rw_1r" + self.names["bitcell_1w_1r"] = "cell_1w_1r" + self.names["dummy_bitcell"] = "dummy_cell_6t" + self.names["dummy_bitcell_1rw_1r"] = "dummy_cell_1rw_1r" + self.names["dummy_bitcell_1w_1r"] = "dummy_cell_1w_1r" + self.names["replica_bitcell"] = "replica_cell_6t" + self.names["replica_bitcell_1rw_1r"] = "replica_cell_1rw_1r" + self.names["replica_bitcell_1w_1r"] = "replica_cell_1w_1r" + self.names["col_cap_bitcell_6t"] = "col_cap_cell_6t" + self.names["col_cap_bitcell_1rw_1r"] = "col_cap_cell_1rw_1r" + self.names["col_cap_bitcell_1w_1r"] = "col_cap_cell_1w_1r" + self.names["row_cap_bitcell_6t"] = "row_cap_cell_6t" + self.names["row_cap_bitcell_1rw_1r"] = "row_cap_cell_1rw_1r" + self.names["row_cap_bitcell_1w_1r"] = "row_cap_cell_1w_1r" self._bitcell = _bitcell._default() diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index fb5e4929..b2a96356 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -7,7 +7,6 @@ # import debug from tech import cell_properties as props -from globals import OPTS import bitcell_base @@ -27,10 +26,8 @@ class bitcell(bitcell_base.bitcell_base): type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Q_bar'] - def __init__(self, name, cell_name=None): - if not cell_name: - cell_name = OPTS.bitcell_name - super().__init__(name, cell_name) + def __init__(self, name): + super().__init__(name) debug.info(2, "Create bitcell") self.nets_match = self.do_nets_exist(self.storage_nets) diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py index a22e511b..9c1d3425 100644 --- a/compiler/bitcells/bitcell_1rw_1r.py +++ b/compiler/bitcells/bitcell_1rw_1r.py @@ -8,7 +8,6 @@ import debug from tech import cell_properties as props import bitcell_base -from globals import OPTS class bitcell_1rw_1r(bitcell_base.bitcell_base): @@ -31,10 +30,8 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base): "INPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Q_bar'] - def __init__(self, name, cell_name=None): - if not cell_name: - cell_name = OPTS.bitcell_name - super().__init__(name, cell_name) + def __init__(self, name): + super().__init__(name) debug.info(2, "Create bitcell with 1RW and 1R Port") self.nets_match = self.do_nets_exist(self.storage_nets) diff --git a/compiler/bitcells/bitcell_1w_1r.py b/compiler/bitcells/bitcell_1w_1r.py index 02b6e768..64a629a2 100644 --- a/compiler/bitcells/bitcell_1w_1r.py +++ b/compiler/bitcells/bitcell_1w_1r.py @@ -8,7 +8,6 @@ import debug from tech import cell_properties as props import bitcell_base -from globals import OPTS class bitcell_1w_1r(bitcell_base.bitcell_base): @@ -31,10 +30,8 @@ class bitcell_1w_1r(bitcell_base.bitcell_base): "INPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Q_bar'] - def __init__(self, name, cell_name=None): - if not cell_name: - cell_name = OPTS.bitcell_name - super().__init__(name, cell_name) + def __init__(self, name): + super().__init__(name) debug.info(2, "Create bitcell with 1W and 1R Port") self.nets_match = self.do_nets_exist(self.storage_nets) diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index f61805da..5ae468b2 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -20,15 +20,15 @@ class bitcell_base(design.design): """ cell_size_layer = "boundary" - def __init__(self, name, cell_name, hard_cell=True): - design.design.__init__(self, name, cell_name) + def __init__(self, name, hard_cell=True): + design.design.__init__(self, name) if hard_cell: - (self.width, self.height) = utils.get_libcell_size(cell_name, + (self.width, self.height) = utils.get_libcell_size(self.cell_name, GDS["unit"], layer[self.cell_size_layer]) self.pin_map = utils.get_libcell_pins(self.pin_names, - cell_name, + self.cell_name, GDS["unit"]) self.add_pin_types(self.type_list) diff --git a/compiler/bitcells/col_cap_bitcell_1rw_1r.py b/compiler/bitcells/col_cap_bitcell_1rw_1r.py index 1f2a30d0..910e25ea 100644 --- a/compiler/bitcells/col_cap_bitcell_1rw_1r.py +++ b/compiler/bitcells/col_cap_bitcell_1rw_1r.py @@ -12,7 +12,8 @@ import bitcell_base class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base): """ - todo""" + Column end cap cell. + """ pin_names = [props.bitcell.cell_1rw1r.pin.bl0, props.bitcell.cell_1rw1r.pin.br0, @@ -22,11 +23,8 @@ class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base): type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "POWER", "GROUND"] - def __init__(self, name="col_cap_cell_1rw_1r", cell_name=None): - if not cell_name: - cell_name = name - # Ignore the name argument - bitcell_base.bitcell_base.__init__(self, name, cell_name) + def __init__(self, name="col_cap_cell_1rw_1r"): + bitcell_base.bitcell_base.__init__(self, name) debug.info(2, "Create col_cap bitcell 1rw+1r object") self.no_instances = True diff --git a/compiler/bitcells/dummy_bitcell.py b/compiler/bitcells/dummy_bitcell.py index 2a3d74ae..679509db 100644 --- a/compiler/bitcells/dummy_bitcell.py +++ b/compiler/bitcells/dummy_bitcell.py @@ -8,7 +8,6 @@ import debug from tech import cell_properties as props import bitcell_base -from globals import OPTS class dummy_bitcell(bitcell_base.bitcell_base): @@ -25,10 +24,8 @@ class dummy_bitcell(bitcell_base.bitcell_base): props.bitcell.cell_6t.pin.gnd] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] - def __init__(self, name, cell_name=None): - if not cell_name: - cell_name = OPTS.dummy_bitcell_name - super().__init__(name, cell_name) + def __init__(self, name): + super().__init__(name) debug.info(2, "Create dummy bitcell") diff --git a/compiler/bitcells/dummy_bitcell_1rw_1r.py b/compiler/bitcells/dummy_bitcell_1rw_1r.py index 0fb92103..8d8a68d2 100644 --- a/compiler/bitcells/dummy_bitcell_1rw_1r.py +++ b/compiler/bitcells/dummy_bitcell_1rw_1r.py @@ -8,7 +8,6 @@ import debug from tech import cell_properties as props import bitcell_base -from globals import OPTS class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base): @@ -29,10 +28,8 @@ class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base): type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] - def __init__(self, name, cell_name=None): - if not cell_name: - cell_name = OPTS.dummy_bitcell_name - super().__init__(name, cell_name) + def __init__(self, name): + super().__init__(name) debug.info(2, "Create dummy bitcell 1rw+1r object") diff --git a/compiler/bitcells/dummy_bitcell_1w_1r.py b/compiler/bitcells/dummy_bitcell_1w_1r.py index 1f3fb754..60d87728 100644 --- a/compiler/bitcells/dummy_bitcell_1w_1r.py +++ b/compiler/bitcells/dummy_bitcell_1w_1r.py @@ -8,7 +8,6 @@ import debug from tech import cell_properties as props import bitcell_base -from globals import OPTS class dummy_bitcell_1w_1r(bitcell_base.bitcell_base): @@ -29,10 +28,8 @@ class dummy_bitcell_1w_1r(bitcell_base.bitcell_base): type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"] - def __init__(self, name, cell_name=None): - if not cell_name: - cell_name = OPTS.dummy_bitcell_name - super().__init__(name, cell_name) + def __init__(self, name): + super().__init__(name) debug.info(2, "Create dummy bitcell 1w+1r object") diff --git a/compiler/bitcells/dummy_pbitcell.py b/compiler/bitcells/dummy_pbitcell.py index 4ece44c4..323f2bc3 100644 --- a/compiler/bitcells/dummy_pbitcell.py +++ b/compiler/bitcells/dummy_pbitcell.py @@ -18,14 +18,12 @@ class dummy_pbitcell(design.design): """ def __init__(self, name, cell_name=None): - if not cell_name: - cell_name = name self.num_rw_ports = OPTS.num_rw_ports self.num_w_ports = OPTS.num_w_ports self.num_r_ports = OPTS.num_r_ports self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports - design.design.__init__(self, name, cell_name) + design.design.__init__(self, name) debug.info(1, "create a dummy bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports, self.num_w_ports, self.num_r_ports)) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index e2cdd032..120bb48e 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -21,9 +21,7 @@ class pbitcell(bitcell_base.bitcell_base): with a variable number of read/write, write, and read ports """ - def __init__(self, name, cell_name=None, replica_bitcell=False, dummy_bitcell=False): - if not cell_name: - cell_name = name + def __init__(self, name, replica_bitcell=False, dummy_bitcell=False): self.num_rw_ports = OPTS.num_rw_ports self.num_w_ports = OPTS.num_w_ports self.num_r_ports = OPTS.num_r_ports @@ -32,7 +30,7 @@ class pbitcell(bitcell_base.bitcell_base): self.replica_bitcell = replica_bitcell self.dummy_bitcell = dummy_bitcell - bitcell_base.bitcell_base.__init__(self, name, cell_name, hard_cell=False) + bitcell_base.bitcell_base.__init__(self, name, hard_cell=False) fmt_str = "{0} rw ports, {1} w ports and {2} r ports" info_string = fmt_str.format(self.num_rw_ports, self.num_w_ports, diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell.py index 53bcd16f..74e121ee 100644 --- a/compiler/bitcells/replica_bitcell.py +++ b/compiler/bitcells/replica_bitcell.py @@ -6,11 +6,10 @@ # All rights reserved. # import debug -import utils import bitcell_base -from tech import GDS, layer from tech import cell_properties as props -from globals import OPTS +from tech import parameter, drc +import logical_effort class replica_bitcell(bitcell_base.bitcell_base): @@ -27,32 +26,29 @@ class replica_bitcell(bitcell_base.bitcell_base): props.bitcell.cell_6t.pin.gnd] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] - def __init__(self, name, cell_name=None): - if not cell_name: - cell_name = OPTS.replica_bitcell_name - # Ignore the name argument - super().__init__(name, cell_name) + def __init__(self, name): + super().__init__(name) debug.info(2, "Create replica bitcell object") def get_stage_effort(self, load): parasitic_delay = 1 - size = 0.5 #This accounts for bitline being drained thought the access TX and internal node - cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file. - read_port_load = 0.5 #min size NMOS gate load - return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False) + size = 0.5 # This accounts for bitline being drained thought the access TX and internal node + cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file. + read_port_load = 0.5 # min size NMOS gate load + return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False) def input_load(self): """Return the relative capacitance of the access transistor gates""" # FIXME: This applies to bitline capacitances as well. - access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] - return 2*access_tx_cin + access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"] + return 2 * access_tx_cin def analytical_power(self, corner, load): """Bitcell power in nW. Only characterizes leakage.""" from tech import spice leakage = spice["bitcell_leakage"] - dynamic = 0 #temporary + dynamic = 0 # FIXME total_power = self.return_power(dynamic, leakage) return total_power diff --git a/compiler/bitcells/replica_bitcell_1rw_1r.py b/compiler/bitcells/replica_bitcell_1rw_1r.py index f2696e19..9dc9aac9 100644 --- a/compiler/bitcells/replica_bitcell_1rw_1r.py +++ b/compiler/bitcells/replica_bitcell_1rw_1r.py @@ -8,7 +8,8 @@ import debug import bitcell_base from tech import cell_properties as props -from globals import OPTS +from tech import parameter, drc +import logical_effort class replica_bitcell_1rw_1r(bitcell_base.bitcell_base): @@ -28,33 +29,31 @@ class replica_bitcell_1rw_1r(bitcell_base.bitcell_base): props.bitcell.cell_1rw1r.pin.gnd] type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] - def __init__(self, name, cell_name=None): - if not cell_name: - cell_name = OPTS.replica_bitcell_name - super().__init__(name, cell_name) + def __init__(self, name): + super().__init__(name) debug.info(2, "Create replica bitcell 1rw+1r object") def get_stage_effort(self, load): parasitic_delay = 1 - size = 0.5 #This accounts for bitline being drained thought the access TX and internal node - cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file. - read_port_load = 0.5 #min size NMOS gate load - return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False) + size = 0.5 # This accounts for bitline being drained thought the access TX and internal node + cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file. + read_port_load = 0.5 # min size NMOS gate load + return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False) def input_load(self): """Return the relative capacitance of the access transistor gates""" # FIXME: This applies to bitline capacitances as well. # FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed. - access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] - return 2*access_tx_cin + access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"] + return 2 * access_tx_cin def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" - pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} + pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} pins = props.bitcell.cell_1rw1r.pin - #Edges hardcoded here. Essentially wl->bl/br for both ports. + # Edges hardcoded here. Essentially wl->bl/br for both ports. # Port 0 edges graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self) graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self) diff --git a/compiler/bitcells/replica_bitcell_1w_1r.py b/compiler/bitcells/replica_bitcell_1w_1r.py index 248292ed..59fa4676 100644 --- a/compiler/bitcells/replica_bitcell_1w_1r.py +++ b/compiler/bitcells/replica_bitcell_1w_1r.py @@ -8,9 +8,8 @@ import debug import bitcell_base from tech import cell_properties as props -from globals import OPTS -from tech import GDS, layer -import utils +from tech import parameter, drc +import logical_effort class replica_bitcell_1w_1r(bitcell_base.bitcell_base): @@ -30,35 +29,32 @@ class replica_bitcell_1w_1r(bitcell_base.bitcell_base): props.bitcell.cell_1w1r.pin.gnd] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"] - def __init__(self, name, cell_name=None): - if not cell_name: - cell_name = OPTS.replica_bitcell_name - super().__init__(name, cell_name) + def __init__(self, name): + super().__init__(name) debug.info(2, "Create replica bitcell 1w+1r object") - def get_stage_effort(self, load): parasitic_delay = 1 - size = 0.5 #This accounts for bitline being drained thought the access TX and internal node - cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file. - read_port_load = 0.5 #min size NMOS gate load - return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False) + size = 0.5 # This accounts for bitline being drained thought the access TX and internal node + cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file. + read_port_load = 0.5 # min size NMOS gate load + return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False) def input_load(self): """Return the relative capacitance of the access transistor gates""" # FIXME: This applies to bitline capacitances as well. # FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed. - access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] - return 2*access_tx_cin + access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"] + return 2 * access_tx_cin def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" - debug.info(1,'Adding edges for {}'.format(inst_name)) - pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} + debug.info(1, 'Adding edges for {}'.format(inst_name)) + pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} pins = props.bitcell.cell_1w1r.pin - #Edges hardcoded here. Essentially wl->bl/br for the read port. + # Edges hardcoded here. Essentially wl->bl/br for the read port. # Port 1 edges graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self) graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self) diff --git a/compiler/bitcells/row_cap_bitcell_1rw_1r.py b/compiler/bitcells/row_cap_bitcell_1rw_1r.py index 17de5d34..6d6dfe16 100644 --- a/compiler/bitcells/row_cap_bitcell_1rw_1r.py +++ b/compiler/bitcells/row_cap_bitcell_1rw_1r.py @@ -12,20 +12,16 @@ import bitcell_base class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base): """ - A single bit cell which is forced to store a 0. - This module implements the single memory cell used in the design. It - is a hand-made cell, so the layout and netlist should be available in - the technology library. """ + Row end cap cell. + """ pin_names = [props.bitcell.cell_1rw1r.pin.wl0, props.bitcell.cell_1rw1r.pin.wl1, props.bitcell.cell_1rw1r.pin.gnd] type_list = ["INPUT", "INPUT", "GROUND"] - def __init__(self, name="row_cap_cell_1rw_1r", cell_name=None): - if not cell_name: - cell_name = name - bitcell_base.bitcell_base.__init__(self, name, cell_name) + def __init__(self, name="row_cap_cell_1rw_1r"): + bitcell_base.bitcell_base.__init__(self, name) debug.info(2, "Create row_cap bitcell 1rw+1r object") self.no_instances = True diff --git a/compiler/debug.py b/compiler/debug.py index f07471cc..15876f22 100644 --- a/compiler/debug.py +++ b/compiler/debug.py @@ -26,9 +26,6 @@ def check(check, str): log("ERROR: file {0}: line {1}: {2}\n".format( os.path.basename(filename), line_number, str)) - if globals.OPTS.debug_level > 0: - import pdb - pdb.set_trace() assert 0 @@ -40,9 +37,6 @@ def error(str, return_value=0): log("ERROR: file {0}: line {1}: {2}\n".format( os.path.basename(filename), line_number, str)) - if globals.OPTS.debug_level > 0 and return_value != 0: - import pdb - pdb.set_trace() assert return_value == 0 diff --git a/compiler/example_configs/riscv-scn4m_subm-16kbyte.py b/compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-16kbyte.py rename to compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-1kbyte.py b/compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-1kbyte.py rename to compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-2kbyte.py b/compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-2kbyte.py rename to compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-4kbyte.py b/compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-4kbyte.py rename to compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-8kbyte.py b/compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-8kbyte.py rename to compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py diff --git a/compiler/example_configs/riscv-sky130-1kbyte-1rw.py b/compiler/example_configs/riscv-sky130-1kbyte-1rw.py new file mode 100644 index 00000000..7d68dbd1 --- /dev/null +++ b/compiler/example_configs/riscv-sky130-1kbyte-1rw.py @@ -0,0 +1,26 @@ +word_size = 32 +num_words = 256 +write_size = 8 + +local_array_size = 16 + +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 + +tech_name = "sky130" +nominal_corner_only = True + +route_supplies = False +check_lvsdrc = True +perimeter_pins = False +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-sky130-1kbyte.py b/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py similarity index 94% rename from compiler/example_configs/riscv-sky130-1kbyte.py rename to compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py index 637505dd..f33ad55a 100644 --- a/compiler/example_configs/riscv-sky130-1kbyte.py +++ b/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py @@ -11,9 +11,9 @@ num_w_ports = 0 tech_name = "sky130" nominal_corner_only = True -route_supplies = True +route_supplies = False check_lvsdrc = True -perimeter_pins = True +perimeter_pins = False #netlist_only = True #analytical_delay = False output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, diff --git a/compiler/example_configs/riscv-sky130-2kbyte-1rw.py b/compiler/example_configs/riscv-sky130-2kbyte-1rw.py new file mode 100644 index 00000000..482eebc5 --- /dev/null +++ b/compiler/example_configs/riscv-sky130-2kbyte-1rw.py @@ -0,0 +1,26 @@ +word_size = 32 +num_words = 512 +write_size = 8 + +local_array_size = 16 + +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 + +tech_name = "sky130" +nominal_corner_only = True + +route_supplies = False +check_lvsdrc = True +perimeter_pins = False +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-sky130-2kbyte.py b/compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py similarity index 94% rename from compiler/example_configs/riscv-sky130-2kbyte.py rename to compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py index cb520b48..c2a90a36 100644 --- a/compiler/example_configs/riscv-sky130-2kbyte.py +++ b/compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py @@ -11,9 +11,9 @@ num_w_ports = 0 tech_name = "sky130" nominal_corner_only = True -route_supplies = True +route_supplies = False check_lvsdrc = True -perimeter_pins = True +perimeter_pins = False #netlist_only = True #analytical_delay = False output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, diff --git a/compiler/example_configs/riscv-sky130-4kbyte-1rw.py b/compiler/example_configs/riscv-sky130-4kbyte-1rw.py new file mode 100644 index 00000000..9e11116e --- /dev/null +++ b/compiler/example_configs/riscv-sky130-4kbyte-1rw.py @@ -0,0 +1,26 @@ +word_size = 32 +num_words = 1024 +write_size = 8 + +local_array_size = 16 + +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 + +tech_name = "sky130" +nominal_corner_only = True + +route_supplies = False +check_lvsdrc = True +perimeter_pins = False +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-sky130-4kbyte.py b/compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py similarity index 94% rename from compiler/example_configs/riscv-sky130-4kbyte.py rename to compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py index 815f2105..2da1c708 100644 --- a/compiler/example_configs/riscv-sky130-4kbyte.py +++ b/compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py @@ -11,9 +11,9 @@ num_w_ports = 0 tech_name = "sky130" nominal_corner_only = True -route_supplies = True +route_supplies = False check_lvsdrc = True -perimeter_pins = True +perimeter_pins = False #netlist_only = True #analytical_delay = False output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, diff --git a/compiler/globals.py b/compiler/globals.py index 9e05efcb..216a6a34 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -208,11 +208,9 @@ def setup_bitcell(): # If we have non-1rw ports, # and the user didn't over-ride the bitcell manually, # figure out the right bitcell to use - if (OPTS.bitcell == "bitcell"): - + if OPTS.bitcell == "bitcell": if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0): OPTS.bitcell = "bitcell" - OPTS.bitcell_name = "cell_6t" else: ports = "" if OPTS.num_rw_ports > 0: @@ -225,20 +223,13 @@ def setup_bitcell(): if ports != "": OPTS.bitcell_suffix = "_" + ports OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix - OPTS.bitcell_name = "cell" + OPTS.bitcell_suffix OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell - OPTS.dummy_bitcell_name = "dummy_" + OPTS.bitcell_name - OPTS.replica_bitcell = "replica_" + OPTS.bitcell - OPTS.replica_bitcell_name = "replica_" + OPTS.bitcell_name - elif (OPTS.bitcell == "pbitcell"): + elif OPTS.bitcell == "pbitcell": OPTS.bitcell = "pbitcell" - OPTS.bitcell_name = "pbitcell" OPTS.dummy_bitcell = "dummy_pbitcell" - OPTS.dummy_bitcell_name = "dummy_pbitcell" OPTS.replica_bitcell = "replica_pbitcell" - OPTS.replica_bitcell_name = "replica_pbitcell" # See if bitcell exists try: @@ -248,11 +239,8 @@ def setup_bitcell(): # or its custom replica bitcell # Use the pbitcell (and give a warning if not in unit test mode) OPTS.bitcell = "pbitcell" - OPTS.bitcell_name = "pbitcell" OPTS.dummy_bitcell = "dummy_pbitcell" - OPTS.dummy_bitcell_name = "dummy_pbitcell" OPTS.replica_bitcell = "replica_pbitcell" - OPTS.replica_bitcell_name = "replica_pbitcell" if not OPTS.is_unit_test: debug.warning("Using the parameterized bitcell which may have suboptimal density.") debug.info(1, "Using bitcell: {}".format(OPTS.bitcell)) @@ -269,8 +257,8 @@ def get_tool(tool_type, preferences, default_name=None): if default_name: exe_name = find_exe(default_name) if exe_name == None: - debug.error("{0} not found. Cannot find {1} tool.".format(default_name, - tool_type), + debug.error("{0} not found. Cannot find {1} tool.".format(default_name, tool_type) + + "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2) else: debug.info(1, "Using {0}: {1}".format(tool_type, exe_name)) @@ -283,8 +271,7 @@ def get_tool(tool_type, preferences, default_name=None): return(name, exe_name) else: debug.info(1, - "Could not find {0}, trying next {1} tool.".format(name, - tool_type)) + "Could not find {0}, trying next {1} tool.".format(name, tool_type)) else: return(None, "") @@ -619,4 +606,4 @@ def report_status(): if OPTS.trim_netlist: debug.print_raw("Trimming netlist to speed up characterization (trim_netlist=False to disable).") if OPTS.nominal_corner_only: - debug.print_raw("Only characterizing nominal corner.") + debug.print_raw("Only generating nominal corner timing.") diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index 28bdfe8d..52393713 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -39,7 +39,7 @@ class sram_config: def compute_sizes(self): """ Computes the organization of the memory using bitcell size by trying to make it square.""" - bitcell = factory.create(module_type=OPTS.bitcell, cell_name=OPTS.bitcell_name) + bitcell = factory.create(module_type=OPTS.bitcell) debug.check(self.num_banks in [1, 2, 4], "Valid number of banks are 1 , 2 and 4.") diff --git a/compiler/tests/00_code_format_check_test.py b/compiler/tests/00_code_format_check_test.py index 834cbace..c66cfab9 100755 --- a/compiler/tests/00_code_format_check_test.py +++ b/compiler/tests/00_code_format_check_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * -import sys,os,re +import sys, os,re sys.path.append(os.getenv("OPENRAM_HOME")) import globals import debug diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index dbdb1cd2..53d50386 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os,re +import sys, os,re #sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index ed15770d..353c1f88 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os,re +import sys, os,re sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 7a43d0e4..e57fc7f4 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index 306bf4e1..a0120c33 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index 0774af4a..f14e4d10 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index 3bf3e293..34fcd3ae 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index 0b24ffd5..8e8eacb9 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 0f0edb9c..44d862c2 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index f7f3db78..4dc2c089 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index 9fae372e..66428404 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/03_ptx_no_contacts_test.py b/compiler/tests/03_ptx_no_contacts_test.py index 58611ca8..d129669b 100755 --- a/compiler/tests/03_ptx_no_contacts_test.py +++ b/compiler/tests/03_ptx_no_contacts_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_and2_dec_test.py b/compiler/tests/04_and2_dec_test.py index de215ffe..f21f848a 100755 --- a/compiler/tests/04_and2_dec_test.py +++ b/compiler/tests/04_and2_dec_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class and2_dec_test(openram_test): def runTest(self): diff --git a/compiler/tests/04_and3_dec_test.py b/compiler/tests/04_and3_dec_test.py index 51a310fd..5a53fc30 100755 --- a/compiler/tests/04_and3_dec_test.py +++ b/compiler/tests/04_and3_dec_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py index f92d2c91..6ea91a72 100755 --- a/compiler/tests/04_dummy_pbitcell_test.py +++ b/compiler/tests/04_dummy_pbitcell_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index 74880a2f..ec8fb4f2 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pbuf_dec_8x_test.py b/compiler/tests/04_pbuf_dec_8x_test.py index 6a7bd62a..9081b336 100755 --- a/compiler/tests/04_pbuf_dec_8x_test.py +++ b/compiler/tests/04_pbuf_dec_8x_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index 7ed92ab8..b3f55749 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index d1d3dad4..3e1a27c2 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pinv_100x_test.py b/compiler/tests/04_pinv_100x_test.py index 91b55d5d..89924710 100755 --- a/compiler/tests/04_pinv_100x_test.py +++ b/compiler/tests/04_pinv_100x_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index f8452460..7ebe88c1 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index 45a6d37c..edae1047 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index 39704975..4ac637e2 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index 374279a1..4022b510 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pinv_dec_1x_test.py b/compiler/tests/04_pinv_dec_1x_test.py index 18f5e907..e683eab3 100755 --- a/compiler/tests/04_pinv_dec_1x_test.py +++ b/compiler/tests/04_pinv_dec_1x_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class pinv_dec_1x_test(openram_test): def runTest(self): diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index df7645d1..02f1bf3d 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index 04106f03..c5695a6f 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index 0a327e86..4ea74269 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index fd6ecab2..85f1930b 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_precharge_1rw_1r_test.py b/compiler/tests/04_precharge_1rw_1r_test.py index ea452e38..7b58ac2e 100755 --- a/compiler/tests/04_precharge_1rw_1r_test.py +++ b/compiler/tests/04_precharge_1rw_1r_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_precharge_pbitcell_test.py b/compiler/tests/04_precharge_pbitcell_test.py index 3eb7628d..03638d8a 100755 --- a/compiler/tests/04_precharge_pbitcell_test.py +++ b/compiler/tests/04_precharge_pbitcell_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index e66329b5..33cc6a80 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 64159906..4aee5a36 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/04_wordline_driver_test.py b/compiler/tests/04_wordline_driver_test.py index 74cfb7a7..7ce53d22 100755 --- a/compiler/tests/04_wordline_driver_test.py +++ b/compiler/tests/04_wordline_driver_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/05_bitcell_array_1rw_1r_test.py b/compiler/tests/05_bitcell_array_1rw_1r_test.py index a1b7a3eb..32207ab5 100755 --- a/compiler/tests/05_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/05_bitcell_array_1rw_1r_test.py @@ -8,14 +8,13 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test") class bitcell_array_1rw_1r_test(openram_test): diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index 9726a4ea..95a0d1fb 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py index 512b6ce0..98db9fdc 100755 --- a/compiler/tests/05_dummy_array_test.py +++ b/compiler/tests/05_dummy_array_test.py @@ -6,7 +6,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index 797f27b1..09e607f3 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py index d7e268f8..1e474e4c 100755 --- a/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_1rw_1r_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py index efa05708..f25462e2 100755 --- a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class hierarchical_decoder_pbitcell_test(openram_test): def runTest(self): diff --git a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py index fbcf15f4..9bb32283 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py index f8825c23..dff3378d 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class hierarchical_predecode2x4_pbitcell_test(openram_test): def runTest(self): diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index c2b51f10..56ffbc20 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py index 2e7361a8..5afa3df3 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py index 87f845ae..3640d422 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class hierarchical_predecode3x8_pbitcell_test(openram_test): def runTest(self): diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index c1471a40..f51f81d6 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/06_hierarchical_predecode4x16_test.py b/compiler/tests/06_hierarchical_predecode4x16_test.py index 3ea60c5d..964de073 100755 --- a/compiler/tests/06_hierarchical_predecode4x16_test.py +++ b/compiler/tests/06_hierarchical_predecode4x16_test.py @@ -16,7 +16,6 @@ from sram_factory import factory import debug -# @unittest.skip("SKIPPING hierarchical_predecode4x16_test") class hierarchical_predecode4x16_test(openram_test): def runTest(self): diff --git a/compiler/tests/08_precharge_array_1rw_1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py index d76e0ee7..c0935e6f 100755 --- a/compiler/tests/08_precharge_array_1rw_1r_test.py +++ b/compiler/tests/08_precharge_array_1rw_1r_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class precharge_1rw_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index 47843ca3..c410a476 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/08_wordline_buffer_array_test.py b/compiler/tests/08_wordline_buffer_array_test.py index a753a21a..50eab534 100755 --- a/compiler/tests/08_wordline_buffer_array_test.py +++ b/compiler/tests/08_wordline_buffer_array_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py index cf1810d8..f4a3af42 100755 --- a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py +++ b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/08_wordline_driver_array_pbitcell_test.py b/compiler/tests/08_wordline_driver_array_pbitcell_test.py index 267aaddf..0f31c688 100755 --- a/compiler/tests/08_wordline_driver_array_pbitcell_test.py +++ b/compiler/tests/08_wordline_driver_array_pbitcell_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/08_wordline_driver_array_test.py b/compiler/tests/08_wordline_driver_array_test.py index 3491cc4f..f433ed91 100755 --- a/compiler/tests/08_wordline_driver_array_test.py +++ b/compiler/tests/08_wordline_driver_array_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/09_sense_amp_array_1rw_1r_test.py b/compiler/tests/09_sense_amp_array_1rw_1r_test.py index a8ed4d2f..9c48d8d5 100755 --- a/compiler/tests/09_sense_amp_array_1rw_1r_test.py +++ b/compiler/tests/09_sense_amp_array_1rw_1r_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class sense_amp_test(openram_test): def runTest(self): diff --git a/compiler/tests/09_sense_amp_array_spare_cols_test.py b/compiler/tests/09_sense_amp_array_spare_cols_test.py index 052aea1e..f9c0a670 100755 --- a/compiler/tests/09_sense_amp_array_spare_cols_test.py +++ b/compiler/tests/09_sense_amp_array_spare_cols_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index c71a75e8..2625ac84 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/10_write_driver_array_1rw_1r_test.py b/compiler/tests/10_write_driver_array_1rw_1r_test.py index 4acbf053..fcf3d32b 100755 --- a/compiler/tests/10_write_driver_array_1rw_1r_test.py +++ b/compiler/tests/10_write_driver_array_1rw_1r_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class write_driver_test(openram_test): def runTest(self): diff --git a/compiler/tests/10_write_driver_array_pbitcell_test.py b/compiler/tests/10_write_driver_array_pbitcell_test.py index 397b3762..7a8e4aad 100755 --- a/compiler/tests/10_write_driver_array_pbitcell_test.py +++ b/compiler/tests/10_write_driver_array_pbitcell_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/10_write_driver_array_spare_cols_test.py b/compiler/tests/10_write_driver_array_spare_cols_test.py index fde478ee..0175057a 100755 --- a/compiler/tests/10_write_driver_array_spare_cols_test.py +++ b/compiler/tests/10_write_driver_array_spare_cols_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 8db26a5a..08365d34 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py index 1331747d..d2a998df 100755 --- a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py +++ b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py @@ -9,7 +9,6 @@ import unittest from testutils import * import sys, os - sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index 9d8798c5..ca3032be 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index 6eb338a5..6121a545 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index 24c00ecb..77aef0ca 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -8,13 +8,15 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + +@unittest.skip("SKIPPING 12_tri_gate_array_test") class tri_gate_array_test(openram_test): def runTest(self): diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index 6930a077..d8d2041f 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py index 54181058..cf66692e 100755 --- a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py @@ -6,13 +6,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class replica_bitcell_array_1rw_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py index d9cf7ac6..98ee0a43 100755 --- a/compiler/tests/14_replica_bitcell_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_test.py @@ -6,7 +6,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/14_replica_column_1rw_1r_test.py b/compiler/tests/14_replica_column_1rw_1r_test.py index f98543a3..d197a234 100755 --- a/compiler/tests/14_replica_column_1rw_1r_test.py +++ b/compiler/tests/14_replica_column_1rw_1r_test.py @@ -6,13 +6,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class replica_column_test(openram_test): def runTest(self): diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py index 8ac5eea9..4701cdca 100755 --- a/compiler/tests/14_replica_column_test.py +++ b/compiler/tests/14_replica_column_test.py @@ -25,12 +25,10 @@ class replica_column_test(openram_test): self.local_check(a) debug.info(2, "Testing replica column for cell_1rw_1r") - globals.setup_bitcell() a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6) self.local_check(a) debug.info(2, "Testing replica column for cell_1rw_1r") - globals.setup_bitcell() a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2) self.local_check(a) diff --git a/compiler/tests/14_replica_pbitcell_array_test.py b/compiler/tests/14_replica_pbitcell_array_test.py index 1cd2d9fc..617b7a3f 100755 --- a/compiler/tests/14_replica_pbitcell_array_test.py +++ b/compiler/tests/14_replica_pbitcell_array_test.py @@ -6,7 +6,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index a660ff55..003807f6 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -12,7 +12,7 @@ Run a regression test on a control_logic import unittest from testutils import header,openram_test -import sys,os +import sys, os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS diff --git a/compiler/tests/16_control_logic_w_test.py b/compiler/tests/16_control_logic_w_test.py index 3bc9f545..2e5656f4 100755 --- a/compiler/tests/16_control_logic_w_test.py +++ b/compiler/tests/16_control_logic_w_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/18_port_address_1rw_1r_test.py b/compiler/tests/18_port_address_1rw_1r_test.py index 3b8da0b7..51fa5078 100755 --- a/compiler/tests/18_port_address_1rw_1r_test.py +++ b/compiler/tests/18_port_address_1rw_1r_test.py @@ -6,7 +6,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/18_port_address_test.py b/compiler/tests/18_port_address_test.py index a3cb9bd9..34a59a19 100755 --- a/compiler/tests/18_port_address_test.py +++ b/compiler/tests/18_port_address_test.py @@ -6,7 +6,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/18_port_data_1rw_1r_test.py b/compiler/tests/18_port_data_1rw_1r_test.py index e8205c1a..409d6dfd 100755 --- a/compiler/tests/18_port_data_1rw_1r_test.py +++ b/compiler/tests/18_port_data_1rw_1r_test.py @@ -6,7 +6,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py index ae305cea..069e9db3 100755 --- a/compiler/tests/18_port_data_test.py +++ b/compiler/tests/18_port_data_test.py @@ -6,7 +6,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py index 1f56bd62..8502576f 100755 --- a/compiler/tests/18_port_data_wmask_1rw_1r_test.py +++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py @@ -7,7 +7,6 @@ import unittest from testutils import * import sys, os - sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/19_bank_select_pbitcell_test.py b/compiler/tests/19_bank_select_pbitcell_test.py index 6bf5929e..0b2d9a36 100755 --- a/compiler/tests/19_bank_select_pbitcell_test.py +++ b/compiler/tests/19_bank_select_pbitcell_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index afec4c3c..becb0fe9 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index c2782954..6d9f4436 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 0e736973..758ad58c 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/19_single_bank_spare_cols_test.py b/compiler/tests/19_single_bank_spare_cols_test.py index 78c8f497..5fcf9a41 100755 --- a/compiler/tests/19_single_bank_spare_cols_test.py +++ b/compiler/tests/19_single_bank_spare_cols_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py index 0137ad61..d494972d 100755 --- a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class single_bank_wmask_1rw_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py index e36bd2df..60b0570d 100755 --- a/compiler/tests/19_single_bank_wmask_test.py +++ b/compiler/tests/19_single_bank_wmask_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py index 23b2d490..896b2a13 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py @@ -16,7 +16,6 @@ from sram_factory import factory import debug -# @unittest.skip("SKIPPING psram_1bank_2mux_1rw_1w_wmask_test, multiport layout not complete") class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): def runTest(self): diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 779118cf..f7af5152 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index f07b70f1..e9ab660d 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index a570c3ed..e711c7ca 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py index 43b64154..73b7fe0a 100755 --- a/compiler/tests/21_ngspice_delay_extra_rows_test.py +++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/21_ngspice_delay_global_test.py b/compiler/tests/21_ngspice_delay_global_test.py index d4cbfafa..3cabb312 100755 --- a/compiler/tests/21_ngspice_delay_global_test.py +++ b/compiler/tests/21_ngspice_delay_global_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 81388ccd..d283482a 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 84ce882b..36a7b5e8 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py index 513f74b2..fbeb08c5 100755 --- a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py @@ -16,7 +16,6 @@ from sram_factory import factory import debug -#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test") class psram_1bank_nomux_func_test(openram_test): def runTest(self): diff --git a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py index 806c7b46..f5573ae2 100755 --- a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py +++ b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py @@ -9,7 +9,6 @@ import unittest from testutils import * import sys, os - sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS @@ -17,7 +16,6 @@ from sram_factory import factory import debug -# @unittest.skip("SKIPPING sram_wmask_1w_1r_func_test") class sram_wmask_1w_1r_func_test(openram_test): def runTest(self): diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 2b5d9234..781ea79b 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os,re +import sys, os,re sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index c502b892..c3dcc11a 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os,re +import sys, os,re sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 6021147c..58dc6e93 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os,re +import sys, os,re sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index b370db8f..4b9e78d5 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os,re +import sys, os,re sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 14ad551f..2178bee8 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index 0d3be92a..cf6fb9c9 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py index 67413bae..890ecb8b 100755 --- a/compiler/tests/26_ngspice_pex_pinv_test.py +++ b/compiler/tests/26_ngspice_pex_pinv_test.py @@ -10,7 +10,7 @@ with Ngspice. """ import unittest from testutils import header,openram_test -import sys,os +import sys, os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index 85d52750..01c62a10 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os,re,shutil +import sys, os,re,shutil sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 9a412ada..88d673b6 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os,re,shutil +import sys, os,re,shutil sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index 4bcf93cc..8da102aa 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -15,7 +15,6 @@ run_pex, repsectively. If there is an error, they should abort and report the er If not, OpenRAM will continue as if nothing happened! """ -import os import debug from globals import OPTS from globals import get_tool @@ -49,7 +48,8 @@ elif "assura"==OPTS.drc_exe[0]: elif "magic"==OPTS.drc_exe[0]: from .magic import run_drc, print_drc_stats else: - debug.warning("Did not find a supported DRC tool.") + debug.error("Did not find a supported DRC tool." + + "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2) if not OPTS.lvs_exe: from .none import run_lvs, print_lvs_stats @@ -60,7 +60,8 @@ elif "assura"==OPTS.lvs_exe[0]: elif "netgen"==OPTS.lvs_exe[0]: from .magic import run_lvs, print_lvs_stats else: - debug.warning("Did not find a supported LVS tool.") + debug.warning("Did not find a supported LVS tool." + + "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2) if not OPTS.pex_exe: @@ -70,7 +71,8 @@ elif "calibre"==OPTS.pex_exe[0]: elif "magic"==OPTS.pex_exe[0]: from .magic import run_pex,print_pex_stats else: - debug.warning("Did not find a supported PEX tool.") + debug.warning("Did not find a supported PEX tool." + + "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2) if OPTS.tech_name == "sky130": if OPTS.magic_exe and "magic"==OPTS.magic_exe[0]: diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 6a559b3d..616818af 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -77,8 +77,7 @@ def write_magic_script(cell_name, extract=False, final_verification=False): f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1])) f.write("gds polygon subcell true\n") f.write("gds warning default\n") - # This causes substrate contacts to not be extracted - f.write("# gds readonly true\n") + f.write("gds readonly true\n") f.write("gds read {}.gds\n".format(cell_name)) f.write("load {}\n".format(cell_name)) # Flatten the cell to get rid of DRCs spanning multiple layers