mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' into s8_single_port
This commit is contained in:
jcirimel
commit
3dd5bd5675
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@ -137,6 +137,21 @@ class cell_properties():
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"""
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def __init__(self):
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self.names = {}
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self.names["bitcell"] = "cell_6t"
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self.names["bitcell_1rw_1r"] = "cell_1rw_1r"
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self.names["bitcell_1w_1r"] = "cell_1w_1r"
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self.names["dummy_bitcell"] = "dummy_cell_6t"
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self.names["dummy_bitcell_1rw_1r"] = "dummy_cell_1rw_1r"
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self.names["dummy_bitcell_1w_1r"] = "dummy_cell_1w_1r"
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self.names["replica_bitcell"] = "replica_cell_6t"
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self.names["replica_bitcell_1rw_1r"] = "replica_cell_1rw_1r"
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self.names["replica_bitcell_1w_1r"] = "replica_cell_1w_1r"
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self.names["col_cap_bitcell_6t"] = "col_cap_cell_6t"
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self.names["col_cap_bitcell_1rw_1r"] = "col_cap_cell_1rw_1r"
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self.names["col_cap_bitcell_1w_1r"] = "col_cap_cell_1w_1r"
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self.names["row_cap_bitcell_6t"] = "row_cap_cell_6t"
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self.names["row_cap_bitcell_1rw_1r"] = "row_cap_cell_1rw_1r"
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self.names["row_cap_bitcell_1w_1r"] = "row_cap_cell_1w_1r"
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self._bitcell = _bitcell._default()
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@ -7,7 +7,6 @@
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#
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import debug
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from tech import cell_properties as props
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from globals import OPTS
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import bitcell_base
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@ -27,10 +26,8 @@ class bitcell(bitcell_base.bitcell_base):
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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storage_nets = ['Q', 'Q_bar']
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def __init__(self, name, cell_name=None):
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if not cell_name:
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cell_name = OPTS.bitcell_name
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super().__init__(name, cell_name)
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def __init__(self, name):
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super().__init__(name)
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debug.info(2, "Create bitcell")
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self.nets_match = self.do_nets_exist(self.storage_nets)
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@ -8,7 +8,6 @@
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import debug
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from tech import cell_properties as props
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import bitcell_base
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from globals import OPTS
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class bitcell_1rw_1r(bitcell_base.bitcell_base):
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@ -31,10 +30,8 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base):
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"INPUT", "INPUT", "POWER", "GROUND"]
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storage_nets = ['Q', 'Q_bar']
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def __init__(self, name, cell_name=None):
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if not cell_name:
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cell_name = OPTS.bitcell_name
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super().__init__(name, cell_name)
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def __init__(self, name):
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super().__init__(name)
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debug.info(2, "Create bitcell with 1RW and 1R Port")
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self.nets_match = self.do_nets_exist(self.storage_nets)
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@ -8,7 +8,6 @@
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import debug
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from tech import cell_properties as props
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import bitcell_base
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from globals import OPTS
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class bitcell_1w_1r(bitcell_base.bitcell_base):
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@ -31,10 +30,8 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
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"INPUT", "INPUT", "POWER", "GROUND"]
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storage_nets = ['Q', 'Q_bar']
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def __init__(self, name, cell_name=None):
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if not cell_name:
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cell_name = OPTS.bitcell_name
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super().__init__(name, cell_name)
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def __init__(self, name):
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super().__init__(name)
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debug.info(2, "Create bitcell with 1W and 1R Port")
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self.nets_match = self.do_nets_exist(self.storage_nets)
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@ -20,15 +20,15 @@ class bitcell_base(design.design):
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"""
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cell_size_layer = "boundary"
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def __init__(self, name, cell_name, hard_cell=True):
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design.design.__init__(self, name, cell_name)
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def __init__(self, name, hard_cell=True):
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design.design.__init__(self, name)
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if hard_cell:
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(self.width, self.height) = utils.get_libcell_size(cell_name,
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(self.width, self.height) = utils.get_libcell_size(self.cell_name,
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GDS["unit"],
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layer[self.cell_size_layer])
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self.pin_map = utils.get_libcell_pins(self.pin_names,
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cell_name,
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self.cell_name,
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GDS["unit"])
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self.add_pin_types(self.type_list)
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@ -12,7 +12,8 @@ import bitcell_base
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class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
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"""
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todo"""
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Column end cap cell.
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"""
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pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
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props.bitcell.cell_1rw1r.pin.br0,
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@ -22,11 +23,8 @@ class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
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type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
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"POWER", "GROUND"]
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def __init__(self, name="col_cap_cell_1rw_1r", cell_name=None):
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if not cell_name:
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cell_name = name
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# Ignore the name argument
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bitcell_base.bitcell_base.__init__(self, name, cell_name)
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def __init__(self, name="col_cap_cell_1rw_1r"):
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bitcell_base.bitcell_base.__init__(self, name)
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debug.info(2, "Create col_cap bitcell 1rw+1r object")
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self.no_instances = True
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@ -8,7 +8,6 @@
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import debug
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from tech import cell_properties as props
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import bitcell_base
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from globals import OPTS
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class dummy_bitcell(bitcell_base.bitcell_base):
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@ -25,10 +24,8 @@ class dummy_bitcell(bitcell_base.bitcell_base):
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props.bitcell.cell_6t.pin.gnd]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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def __init__(self, name, cell_name=None):
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if not cell_name:
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cell_name = OPTS.dummy_bitcell_name
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super().__init__(name, cell_name)
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def __init__(self, name):
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super().__init__(name)
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debug.info(2, "Create dummy bitcell")
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@ -8,7 +8,6 @@
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import debug
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from tech import cell_properties as props
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import bitcell_base
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from globals import OPTS
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class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
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@ -29,10 +28,8 @@ class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
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type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
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"INPUT", "INPUT", "POWER", "GROUND"]
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def __init__(self, name, cell_name=None):
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if not cell_name:
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cell_name = OPTS.dummy_bitcell_name
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super().__init__(name, cell_name)
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def __init__(self, name):
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super().__init__(name)
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debug.info(2, "Create dummy bitcell 1rw+1r object")
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@ -8,7 +8,6 @@
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import debug
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from tech import cell_properties as props
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import bitcell_base
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from globals import OPTS
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class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
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@ -29,10 +28,8 @@ class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
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"INPUT", "INPUT", "POWER", "GROUND"]
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def __init__(self, name, cell_name=None):
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if not cell_name:
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cell_name = OPTS.dummy_bitcell_name
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super().__init__(name, cell_name)
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def __init__(self, name):
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super().__init__(name)
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debug.info(2, "Create dummy bitcell 1w+1r object")
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@ -18,14 +18,12 @@ class dummy_pbitcell(design.design):
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"""
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def __init__(self, name, cell_name=None):
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if not cell_name:
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cell_name = name
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self.num_rw_ports = OPTS.num_rw_ports
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self.num_w_ports = OPTS.num_w_ports
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self.num_r_ports = OPTS.num_r_ports
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self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
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design.design.__init__(self, name, cell_name)
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design.design.__init__(self, name)
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debug.info(1, "create a dummy bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
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self.num_w_ports,
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self.num_r_ports))
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@ -21,9 +21,7 @@ class pbitcell(bitcell_base.bitcell_base):
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with a variable number of read/write, write, and read ports
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"""
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def __init__(self, name, cell_name=None, replica_bitcell=False, dummy_bitcell=False):
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if not cell_name:
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cell_name = name
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def __init__(self, name, replica_bitcell=False, dummy_bitcell=False):
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self.num_rw_ports = OPTS.num_rw_ports
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self.num_w_ports = OPTS.num_w_ports
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self.num_r_ports = OPTS.num_r_ports
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@ -32,7 +30,7 @@ class pbitcell(bitcell_base.bitcell_base):
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self.replica_bitcell = replica_bitcell
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self.dummy_bitcell = dummy_bitcell
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bitcell_base.bitcell_base.__init__(self, name, cell_name, hard_cell=False)
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bitcell_base.bitcell_base.__init__(self, name, hard_cell=False)
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fmt_str = "{0} rw ports, {1} w ports and {2} r ports"
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info_string = fmt_str.format(self.num_rw_ports,
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self.num_w_ports,
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@ -6,11 +6,10 @@
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# All rights reserved.
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#
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import debug
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import utils
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import bitcell_base
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from tech import GDS, layer
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from tech import cell_properties as props
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from globals import OPTS
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from tech import parameter, drc
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import logical_effort
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class replica_bitcell(bitcell_base.bitcell_base):
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@ -27,32 +26,29 @@ class replica_bitcell(bitcell_base.bitcell_base):
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props.bitcell.cell_6t.pin.gnd]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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def __init__(self, name, cell_name=None):
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if not cell_name:
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cell_name = OPTS.replica_bitcell_name
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# Ignore the name argument
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super().__init__(name, cell_name)
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def __init__(self, name):
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super().__init__(name)
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debug.info(2, "Create replica bitcell object")
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def get_stage_effort(self, load):
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parasitic_delay = 1
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size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
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cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
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read_port_load = 0.5 #min size NMOS gate load
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return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
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size = 0.5 # This accounts for bitline being drained thought the access TX and internal node
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cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
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read_port_load = 0.5 # min size NMOS gate load
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return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
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def input_load(self):
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"""Return the relative capacitance of the access transistor gates"""
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# FIXME: This applies to bitline capacitances as well.
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access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
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return 2*access_tx_cin
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access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
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return 2 * access_tx_cin
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def analytical_power(self, corner, load):
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"""Bitcell power in nW. Only characterizes leakage."""
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from tech import spice
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leakage = spice["bitcell_leakage"]
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dynamic = 0 #temporary
|
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dynamic = 0 # FIXME
|
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total_power = self.return_power(dynamic, leakage)
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return total_power
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||||
|
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|
|
|
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|
|
@ -8,7 +8,8 @@
|
|||
import debug
|
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import bitcell_base
|
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from tech import cell_properties as props
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from globals import OPTS
|
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from tech import parameter, drc
|
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import logical_effort
|
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|
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class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
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|
@ -28,33 +29,31 @@ class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
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props.bitcell.cell_1rw1r.pin.gnd]
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type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
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|
||||
def __init__(self, name, cell_name=None):
|
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if not cell_name:
|
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cell_name = OPTS.replica_bitcell_name
|
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super().__init__(name, cell_name)
|
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def __init__(self, name):
|
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super().__init__(name)
|
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debug.info(2, "Create replica bitcell 1rw+1r object")
|
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|
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def get_stage_effort(self, load):
|
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parasitic_delay = 1
|
||||
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
|
||||
cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
|
||||
read_port_load = 0.5 #min size NMOS gate load
|
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return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
|
||||
size = 0.5 # This accounts for bitline being drained thought the access TX and internal node
|
||||
cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
|
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read_port_load = 0.5 # min size NMOS gate load
|
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return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
|
||||
|
||||
def input_load(self):
|
||||
"""Return the relative capacitance of the access transistor gates"""
|
||||
|
||||
# FIXME: This applies to bitline capacitances as well.
|
||||
# FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
|
||||
access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
|
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return 2*access_tx_cin
|
||||
access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
|
||||
return 2 * access_tx_cin
|
||||
|
||||
def build_graph(self, graph, inst_name, port_nets):
|
||||
"""Adds edges to graph. Multiport bitcell timing graph is too complex
|
||||
to use the add_graph_edges function."""
|
||||
pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
|
||||
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
|
||||
pins = props.bitcell.cell_1rw1r.pin
|
||||
#Edges hardcoded here. Essentially wl->bl/br for both ports.
|
||||
# Edges hardcoded here. Essentially wl->bl/br for both ports.
|
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# Port 0 edges
|
||||
graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)
|
||||
graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self)
|
||||
|
|
|
|||
|
|
@ -8,9 +8,8 @@
|
|||
import debug
|
||||
import bitcell_base
|
||||
from tech import cell_properties as props
|
||||
from globals import OPTS
|
||||
from tech import GDS, layer
|
||||
import utils
|
||||
from tech import parameter, drc
|
||||
import logical_effort
|
||||
|
||||
|
||||
class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
|
||||
|
|
@ -30,35 +29,32 @@ class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
|
|||
props.bitcell.cell_1w1r.pin.gnd]
|
||||
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"]
|
||||
|
||||
def __init__(self, name, cell_name=None):
|
||||
if not cell_name:
|
||||
cell_name = OPTS.replica_bitcell_name
|
||||
super().__init__(name, cell_name)
|
||||
def __init__(self, name):
|
||||
super().__init__(name)
|
||||
debug.info(2, "Create replica bitcell 1w+1r object")
|
||||
|
||||
|
||||
def get_stage_effort(self, load):
|
||||
parasitic_delay = 1
|
||||
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
|
||||
cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
|
||||
read_port_load = 0.5 #min size NMOS gate load
|
||||
return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
|
||||
size = 0.5 # This accounts for bitline being drained thought the access TX and internal node
|
||||
cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
|
||||
read_port_load = 0.5 # min size NMOS gate load
|
||||
return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
|
||||
|
||||
def input_load(self):
|
||||
"""Return the relative capacitance of the access transistor gates"""
|
||||
|
||||
# FIXME: This applies to bitline capacitances as well.
|
||||
# FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
|
||||
access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
|
||||
return 2*access_tx_cin
|
||||
access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
|
||||
return 2 * access_tx_cin
|
||||
|
||||
def build_graph(self, graph, inst_name, port_nets):
|
||||
"""Adds edges to graph. Multiport bitcell timing graph is too complex
|
||||
to use the add_graph_edges function."""
|
||||
debug.info(1,'Adding edges for {}'.format(inst_name))
|
||||
pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
|
||||
debug.info(1, 'Adding edges for {}'.format(inst_name))
|
||||
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
|
||||
pins = props.bitcell.cell_1w1r.pin
|
||||
#Edges hardcoded here. Essentially wl->bl/br for the read port.
|
||||
# Edges hardcoded here. Essentially wl->bl/br for the read port.
|
||||
# Port 1 edges
|
||||
graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
|
||||
graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)
|
||||
|
|
|
|||
|
|
@ -12,20 +12,16 @@ import bitcell_base
|
|||
|
||||
class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
|
||||
"""
|
||||
A single bit cell which is forced to store a 0.
|
||||
This module implements the single memory cell used in the design. It
|
||||
is a hand-made cell, so the layout and netlist should be available in
|
||||
the technology library. """
|
||||
Row end cap cell.
|
||||
"""
|
||||
|
||||
pin_names = [props.bitcell.cell_1rw1r.pin.wl0,
|
||||
props.bitcell.cell_1rw1r.pin.wl1,
|
||||
props.bitcell.cell_1rw1r.pin.gnd]
|
||||
type_list = ["INPUT", "INPUT", "GROUND"]
|
||||
|
||||
def __init__(self, name="row_cap_cell_1rw_1r", cell_name=None):
|
||||
if not cell_name:
|
||||
cell_name = name
|
||||
bitcell_base.bitcell_base.__init__(self, name, cell_name)
|
||||
def __init__(self, name="row_cap_cell_1rw_1r"):
|
||||
bitcell_base.bitcell_base.__init__(self, name)
|
||||
debug.info(2, "Create row_cap bitcell 1rw+1r object")
|
||||
|
||||
self.no_instances = True
|
||||
|
|
|
|||
|
|
@ -26,9 +26,6 @@ def check(check, str):
|
|||
log("ERROR: file {0}: line {1}: {2}\n".format(
|
||||
os.path.basename(filename), line_number, str))
|
||||
|
||||
if globals.OPTS.debug_level > 0:
|
||||
import pdb
|
||||
pdb.set_trace()
|
||||
assert 0
|
||||
|
||||
|
||||
|
|
@ -40,9 +37,6 @@ def error(str, return_value=0):
|
|||
log("ERROR: file {0}: line {1}: {2}\n".format(
|
||||
os.path.basename(filename), line_number, str))
|
||||
|
||||
if globals.OPTS.debug_level > 0 and return_value != 0:
|
||||
import pdb
|
||||
pdb.set_trace()
|
||||
assert return_value == 0
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,26 @@
|
|||
word_size = 32
|
||||
num_words = 256
|
||||
write_size = 8
|
||||
|
||||
local_array_size = 16
|
||||
|
||||
num_rw_ports = 1
|
||||
num_r_ports = 0
|
||||
num_w_ports = 0
|
||||
|
||||
tech_name = "sky130"
|
||||
nominal_corner_only = True
|
||||
|
||||
route_supplies = False
|
||||
check_lvsdrc = True
|
||||
perimeter_pins = False
|
||||
#netlist_only = True
|
||||
#analytical_delay = False
|
||||
output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
|
||||
num_words,
|
||||
write_size,
|
||||
tech_name)
|
||||
output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
|
||||
num_words,
|
||||
write_size,
|
||||
tech_name)
|
||||
|
|
@ -11,9 +11,9 @@ num_w_ports = 0
|
|||
tech_name = "sky130"
|
||||
nominal_corner_only = True
|
||||
|
||||
route_supplies = True
|
||||
route_supplies = False
|
||||
check_lvsdrc = True
|
||||
perimeter_pins = True
|
||||
perimeter_pins = False
|
||||
#netlist_only = True
|
||||
#analytical_delay = False
|
||||
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
word_size = 32
|
||||
num_words = 512
|
||||
write_size = 8
|
||||
|
||||
local_array_size = 16
|
||||
|
||||
num_rw_ports = 1
|
||||
num_r_ports = 0
|
||||
num_w_ports = 0
|
||||
|
||||
tech_name = "sky130"
|
||||
nominal_corner_only = True
|
||||
|
||||
route_supplies = False
|
||||
check_lvsdrc = True
|
||||
perimeter_pins = False
|
||||
#netlist_only = True
|
||||
#analytical_delay = False
|
||||
output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
|
||||
num_words,
|
||||
write_size,
|
||||
tech_name)
|
||||
output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
|
||||
num_words,
|
||||
write_size,
|
||||
tech_name)
|
||||
|
|
@ -11,9 +11,9 @@ num_w_ports = 0
|
|||
tech_name = "sky130"
|
||||
nominal_corner_only = True
|
||||
|
||||
route_supplies = True
|
||||
route_supplies = False
|
||||
check_lvsdrc = True
|
||||
perimeter_pins = True
|
||||
perimeter_pins = False
|
||||
#netlist_only = True
|
||||
#analytical_delay = False
|
||||
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
word_size = 32
|
||||
num_words = 1024
|
||||
write_size = 8
|
||||
|
||||
local_array_size = 16
|
||||
|
||||
num_rw_ports = 1
|
||||
num_r_ports = 0
|
||||
num_w_ports = 0
|
||||
|
||||
tech_name = "sky130"
|
||||
nominal_corner_only = True
|
||||
|
||||
route_supplies = False
|
||||
check_lvsdrc = True
|
||||
perimeter_pins = False
|
||||
#netlist_only = True
|
||||
#analytical_delay = False
|
||||
output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
|
||||
num_words,
|
||||
write_size,
|
||||
tech_name)
|
||||
output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
|
||||
num_words,
|
||||
write_size,
|
||||
tech_name)
|
||||
|
|
@ -11,9 +11,9 @@ num_w_ports = 0
|
|||
tech_name = "sky130"
|
||||
nominal_corner_only = True
|
||||
|
||||
route_supplies = True
|
||||
route_supplies = False
|
||||
check_lvsdrc = True
|
||||
perimeter_pins = True
|
||||
perimeter_pins = False
|
||||
#netlist_only = True
|
||||
#analytical_delay = False
|
||||
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
|
||||
|
|
@ -208,11 +208,9 @@ def setup_bitcell():
|
|||
# If we have non-1rw ports,
|
||||
# and the user didn't over-ride the bitcell manually,
|
||||
# figure out the right bitcell to use
|
||||
if (OPTS.bitcell == "bitcell"):
|
||||
|
||||
if OPTS.bitcell == "bitcell":
|
||||
if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0):
|
||||
OPTS.bitcell = "bitcell"
|
||||
OPTS.bitcell_name = "cell_6t"
|
||||
else:
|
||||
ports = ""
|
||||
if OPTS.num_rw_ports > 0:
|
||||
|
|
@ -225,20 +223,13 @@ def setup_bitcell():
|
|||
if ports != "":
|
||||
OPTS.bitcell_suffix = "_" + ports
|
||||
OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix
|
||||
OPTS.bitcell_name = "cell" + OPTS.bitcell_suffix
|
||||
|
||||
OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell
|
||||
OPTS.dummy_bitcell_name = "dummy_" + OPTS.bitcell_name
|
||||
|
||||
OPTS.replica_bitcell = "replica_" + OPTS.bitcell
|
||||
OPTS.replica_bitcell_name = "replica_" + OPTS.bitcell_name
|
||||
elif (OPTS.bitcell == "pbitcell"):
|
||||
elif OPTS.bitcell == "pbitcell":
|
||||
OPTS.bitcell = "pbitcell"
|
||||
OPTS.bitcell_name = "pbitcell"
|
||||
OPTS.dummy_bitcell = "dummy_pbitcell"
|
||||
OPTS.dummy_bitcell_name = "dummy_pbitcell"
|
||||
OPTS.replica_bitcell = "replica_pbitcell"
|
||||
OPTS.replica_bitcell_name = "replica_pbitcell"
|
||||
|
||||
# See if bitcell exists
|
||||
try:
|
||||
|
|
@ -248,11 +239,8 @@ def setup_bitcell():
|
|||
# or its custom replica bitcell
|
||||
# Use the pbitcell (and give a warning if not in unit test mode)
|
||||
OPTS.bitcell = "pbitcell"
|
||||
OPTS.bitcell_name = "pbitcell"
|
||||
OPTS.dummy_bitcell = "dummy_pbitcell"
|
||||
OPTS.dummy_bitcell_name = "dummy_pbitcell"
|
||||
OPTS.replica_bitcell = "replica_pbitcell"
|
||||
OPTS.replica_bitcell_name = "replica_pbitcell"
|
||||
if not OPTS.is_unit_test:
|
||||
debug.warning("Using the parameterized bitcell which may have suboptimal density.")
|
||||
debug.info(1, "Using bitcell: {}".format(OPTS.bitcell))
|
||||
|
|
@ -269,8 +257,8 @@ def get_tool(tool_type, preferences, default_name=None):
|
|||
if default_name:
|
||||
exe_name = find_exe(default_name)
|
||||
if exe_name == None:
|
||||
debug.error("{0} not found. Cannot find {1} tool.".format(default_name,
|
||||
tool_type),
|
||||
debug.error("{0} not found. Cannot find {1} tool.".format(default_name, tool_type)
|
||||
+ "Disable DRC/LVS with check_lvsdrc=False to ignore.",
|
||||
2)
|
||||
else:
|
||||
debug.info(1, "Using {0}: {1}".format(tool_type, exe_name))
|
||||
|
|
@ -283,8 +271,7 @@ def get_tool(tool_type, preferences, default_name=None):
|
|||
return(name, exe_name)
|
||||
else:
|
||||
debug.info(1,
|
||||
"Could not find {0}, trying next {1} tool.".format(name,
|
||||
tool_type))
|
||||
"Could not find {0}, trying next {1} tool.".format(name, tool_type))
|
||||
else:
|
||||
return(None, "")
|
||||
|
||||
|
|
@ -619,4 +606,4 @@ def report_status():
|
|||
if OPTS.trim_netlist:
|
||||
debug.print_raw("Trimming netlist to speed up characterization (trim_netlist=False to disable).")
|
||||
if OPTS.nominal_corner_only:
|
||||
debug.print_raw("Only characterizing nominal corner.")
|
||||
debug.print_raw("Only generating nominal corner timing.")
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ class sram_config:
|
|||
def compute_sizes(self):
|
||||
""" Computes the organization of the memory using bitcell size by trying to make it square."""
|
||||
|
||||
bitcell = factory.create(module_type=OPTS.bitcell, cell_name=OPTS.bitcell_name)
|
||||
bitcell = factory.create(module_type=OPTS.bitcell)
|
||||
|
||||
debug.check(self.num_banks in [1, 2, 4],
|
||||
"Valid number of banks are 1 , 2 and 4.")
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os,re
|
||||
import sys, os,re
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
import debug
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os,re
|
||||
import sys, os,re
|
||||
#sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os,re
|
||||
import sys, os,re
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,13 +8,14 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class and2_dec_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,13 +8,14 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class pinv_dec_1x_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,14 +8,13 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
|
||||
|
||||
class bitcell_array_1rw_1r_test(openram_test):
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,13 +8,14 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class hierarchical_decoder_pbitcell_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,13 +8,14 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class hierarchical_predecode2x4_pbitcell_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,13 +8,14 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class hierarchical_predecode3x8_pbitcell_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ from sram_factory import factory
|
|||
import debug
|
||||
|
||||
|
||||
# @unittest.skip("SKIPPING hierarchical_predecode4x16_test")
|
||||
class hierarchical_predecode4x16_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,13 +8,14 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class precharge_1rw_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,13 +8,14 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class sense_amp_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,13 +8,14 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class write_driver_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@
|
|||
import unittest
|
||||
from testutils import *
|
||||
import sys, os
|
||||
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -8,13 +8,15 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
@unittest.skip("SKIPPING 12_tri_gate_array_test")
|
||||
class tri_gate_array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -6,13 +6,14 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class replica_bitcell_array_1rw_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -6,13 +6,14 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class replica_column_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -25,12 +25,10 @@ class replica_column_test(openram_test):
|
|||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing replica column for cell_1rw_1r")
|
||||
globals.setup_bitcell()
|
||||
a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing replica column for cell_1rw_1r")
|
||||
globals.setup_bitcell()
|
||||
a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2)
|
||||
self.local_check(a)
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ Run a regression test on a control_logic
|
|||
|
||||
import unittest
|
||||
from testutils import header,openram_test
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
|
|
|
|||
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Reference in New Issue