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fixing named variables passed between array modules

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samuelkcrow
2023-02-04 21:06:41 -08:00
parent 2f795f8068
commit 3dac89d041
3 changed files with 29 additions and 16 deletions
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compiler/modules/replica_bitcell_array.py
+2 -3
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@@ -182,10 +182,9 @@ class replica_bitcell_array(bitcell_base_array):
self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
self.bitcell_wordline_names = self.bitcell_array.wordline_names
self.all_bitcell_wordline_names = self.bitcell_array.all_wordline_names
# All wordlines including RBL
self.all_wordline_names = []
# All wordlines including RBL self.all_wordline_names = []
for bit in range(self.rbl[0]):
self.all_wordline_names.extend(self.rbl_wordline_names[bit])
self.all_wordline_names.extend(self.all_bitcell_wordline_names)