diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py index fb4a078b..8f7fb28d 100644 --- a/compiler/modules/capped_replica_bitcell_array.py +++ b/compiler/modules/capped_replica_bitcell_array.py @@ -155,15 +155,28 @@ class capped_replica_bitcell_array(bitcell_base_array): self.add_pin("gnd", "GROUND") def add_bitline_pins(self): - self.all_bitline_names = self.replica_bitcell_array.all_bitline_names - self.replica_array_bitline_names = self.replica_bitcell_array.all_bitline_names + # some of these are just included for compatibility with modules instantiating this module + self.bitcell_bitline_names = self.replica_bitcell_array.bitcell_bitline_names + self.all_bitcell_bitline_names = self.replica_bitcell_array.all_bitcell_bitline_names + self.rbl_bitline_names = self.replica_bitcell_array.rbl_bitline_names + self.all_rbl_bitline_names = self.replica_bitcell_array.all_rbl_bitline_names - self.add_pin_list(self.replica_array_bitline_names, "INOUT") + self.bitline_names = self.replica_bitcell_array.bitline_names + self.all_bitline_names = self.replica_bitcell_array.all_bitline_names + + self.add_pin_list(self.all_bitline_names, "INOUT") def add_wordline_pins(self): + # some of these are just included for compatibility with modules instantiating this module + self.rbl_wordline_names = self.replica_bitcell_array.rbl_wordline_names + self.all_rbl_wordline_names = self.replica_bitcell_array.all_rbl_wordline_names + self.bitcell_wordline_names = self.replica_bitcell_array.wordline_names + self.all_bitcell_wordline_names = self.replica_bitcell_array.all_wordline_names + self.used_wordline_names = self.replica_bitcell_array.used_wordline_names self.unused_wordline_names = self.replica_bitcell_array.unused_wordline_names self.replica_array_wordline_names = self.replica_bitcell_array.all_wordline_names + self.replica_array_all_wordline_names = self.replica_bitcell_array.wordline_names self.replica_array_wordline_names_with_grounded_wls = ["gnd" if x in self.unused_wordline_names else x for x in self.replica_array_wordline_names] self.all_wordline_names = [] @@ -180,7 +193,7 @@ class capped_replica_bitcell_array(bitcell_base_array): # Main array self.replica_bitcell_array_inst=self.add_inst(name="replica_bitcell_array", mod=self.replica_bitcell_array) - self.connect_inst(self.replica_array_bitline_names + self.replica_array_wordline_names_with_grounded_wls + self.supplies) + self.connect_inst(self.all_bitline_names + self.replica_array_wordline_names_with_grounded_wls + self.supplies) # Top/bottom dummy rows or col caps self.dummy_row_insts = [] @@ -243,6 +256,7 @@ class capped_replica_bitcell_array(bitcell_base_array): self.DRC_LVS() + # TODO: I think I gotta offset these to account for the stupid instances not knowing where they are def get_main_array_top(self): return self.replica_bitcell_array_inst.get_main_array_top() diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index 656568db..00206730 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -19,7 +19,7 @@ class local_bitcell_array(bitcell_base_array): This can either be a single aray on its own if there is no hierarchical WL or it can be combined into a larger array with hierarchical WL. """ - def __init__(self, rows, cols, rbl, left_rbl=[], right_rbl=[], name=""): + def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""): super().__init__(name=name, rows=rows, cols=cols, column_offset=0) debug.info(2, "Creating {0} {1}x{2} rbl: {3} left_rbl: {4} right_rbl: {5}".format(name, rows, @@ -84,11 +84,11 @@ class local_bitcell_array(bitcell_base_array): # Inputs to the bitcell array (by port) self.array_wordline_inputs = [] - self.wordline_names = self.bitcell_array.wordline_names - self.all_wordline_names = self.bitcell_array.all_wordline_names + self.wordline_names = self.bitcell_array.bitcell_wordline_names + self.all_wordline_names = self.bitcell_array.bitcell_all_wordline_names - self.bitline_names = self.bitcell_array.bitline_names - self.all_bitline_names = self.bitcell_array.all_bitline_names + self.bitline_names = self.bitcell_array.bitcell_bitline_names + self.all_bitline_names = self.bitcell_array.all_bitcell_bitline_names self.rbl_wordline_names = self.bitcell_array.rbl_wordline_names self.all_rbl_wordline_names = self.bitcell_array.all_rbl_wordline_names @@ -163,7 +163,7 @@ class local_bitcell_array(bitcell_base_array): # FIXME: Replace this with a tech specific parameter driver_to_array_spacing = 3 * self.m3_pitch - wl_offset = vector(0, self.bitcell_array.get_replica_bottom()) + wl_offset = vector(0, self.bitcell_array.get_replica_bottom()) # look for offset problems here self.wl_insts[0].place(wl_offset) bitcell_array_offset = vector(self.wl_insts[0].rx() + driver_to_array_spacing, 0) @@ -171,7 +171,7 @@ class local_bitcell_array(bitcell_base_array): if len(self.all_ports) > 1: wl_offset = vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing, - self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height) + self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height) # look for offset problems here self.wl_insts[1].place(wl_offset, mirror="XY") @@ -273,7 +273,7 @@ class local_bitcell_array(bitcell_base_array): def get_main_array_right(self): return self.bitcell_array_inst.lx() + self.bitcell_array.get_main_array_right() - def get_column_offsets(self): + def get_column_offsets(self): # TODO: copy this style when fixing getters in capped_replica_bitcell_array.py """ Return an array of the x offsets of all the regular bits """ @@ -294,7 +294,7 @@ class local_bitcell_array(bitcell_base_array): self.bitcell_array.graph_exclude_replica_col_bits() - def get_cell_name(self, inst_name, row, col): + def get_cell_name(self, inst_name, row, col): # TODO: no shot this'll work... """Gets the spice name of the target bitcell.""" return self.bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index b6eabc3d..2211bd55 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -182,10 +182,9 @@ class replica_bitcell_array(bitcell_base_array): self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl] + self.bitcell_wordline_names = self.bitcell_array.wordline_names self.all_bitcell_wordline_names = self.bitcell_array.all_wordline_names - - # All wordlines including RBL - self.all_wordline_names = [] +# All wordlines including RBL self.all_wordline_names = [] for bit in range(self.rbl[0]): self.all_wordline_names.extend(self.rbl_wordline_names[bit]) self.all_wordline_names.extend(self.all_bitcell_wordline_names)