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Fix missing via LVS issues. LVS passing for some 20 tests.

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This commit is contained in:
mrg
2020-07-01 09:22:59 -07:00
parent b07f30cb9e
commit 3d0f29ff3a
4 changed files with 53 additions and 33 deletions
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compiler/sram/sram_1bank.py
+6 -1
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@@ -457,7 +457,12 @@ class sram_1bank(sram_base):
dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))
self.add_wire(self.m2_stack[::-1],
[src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()])
# self.connect_hbus(src_pin, dest_pin)
self.add_via_stack_center(from_layer=src_pin.layer,
to_layer="m2",
offset=src_pin.center())
self.add_via_stack_center(from_layer=dest_pin.layer,
to_layer="m2",
offset=dest_pin.center())
def route_row_addr_dff(self):
""" Connect the output of the row flops to the bank pins """