diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index a5272ba5..275b69e9 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -917,8 +917,10 @@ class layout(): (horizontal_layer, via_layer, vertical_layer) = layer_stack if horizontal: route_layer = vertical_layer + bys_layer = horizontal_layer else: route_layer = horizontal_layer + bus_layer = vertical_layer for (pin_name, bus_name) in mapping: pin = inst.get_pin(pin_name) @@ -940,17 +942,18 @@ class layout(): # Connect to the pin on the instances with a via if it is # not on the right layer if pin.layer != route_layer: - self.add_via_center(layers=layer_stack, - offset=pin_pos) + self.add_via_stack_center(from_layer=pin.layer, + to_layer=route_layer, + offset=pin_pos) # FIXME: output pins tend to not be rotate, # but supply pins are. Make consistent? # We only need a via if they happened to align perfectly # so the add_wire didn't add a via if (horizontal and bus_pos.y == pin_pos.y) or (not horizontal and bus_pos.x == pin_pos.x): - self.add_via_center(layers=layer_stack, - offset=bus_pos, - rotate=90) + self.add_via_stack_center(from_layer=route_layer, + to_layer=bus_layer, + offset=bus_pos) def connect_vbus(self, src_pin, dest_pin, hlayer="m3", vlayer="m2"): """ diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 78215d49..020b90ec 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -555,9 +555,15 @@ class control_logic(design.design): clkbuf_map = zip(["A"], ["clk_buf"]) self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.input_bus) - out_pos = self.clk_bar_inst.get_pin("Z").center() - in_pos = self.gated_clk_bar_inst.get_pin("A").center() - self.add_zjog("m1", out_pos, in_pos) + out_pin = self.clk_bar_inst.get_pin("Z") + out_pos = out_pin.center() + in_pin = self.gated_clk_bar_inst.get_pin("A") + in_pos = in_pin.center() + self.add_zjog(out_pin.layer, out_pos, in_pos) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer=in_pin.layer, + offset=in_pos) + # This is the second gate over, so it needs to be on M3 clkbuf_map = zip(["B"], ["cs"]) @@ -809,23 +815,27 @@ class control_logic(design.design): def route_supply(self): """ Add vdd and gnd to the instance cells """ + if OPTS.tech_name == "sky130": + supply_layer = "li" + else: + supply_layer = "m1" max_row_x_loc = max([inst.rx() for inst in self.row_end_inst]) for inst in self.row_end_inst: pins = inst.get_pins("vdd") for pin in pins: - if pin.layer == "m1": + if pin.layer == supply_layer: row_loc = pin.rc() pin_loc = vector(max_row_x_loc, pin.rc().y) - self.add_power_pin("vdd", pin_loc) - self.add_path("m1", [row_loc, pin_loc]) + self.add_power_pin("vdd", pin_loc, start_layer=pin.layer) + self.add_path(supply_layer, [row_loc, pin_loc]) pins = inst.get_pins("gnd") for pin in pins: - if pin.layer == "m1": + if pin.layer == supply_layer: row_loc = pin.rc() pin_loc = vector(max_row_x_loc, pin.rc().y) - self.add_power_pin("gnd", pin_loc) - self.add_path("m1", [row_loc, pin_loc]) + self.add_power_pin("gnd", pin_loc, start_layer=pin.layer) + self.add_path(supply_layer, [row_loc, pin_loc]) self.copy_layout_pin(self.delay_inst, "gnd") self.copy_layout_pin(self.delay_inst, "vdd") @@ -1008,12 +1018,13 @@ class control_logic(design.design): def route_output_to_bus_jogged(self, inst, name): # Connect this at the bottom of the buffer - out_pos = inst.get_pin("Z").center() + out_pin = inst.get_pin("Z") + out_pos = out_pin.center() mid1 = vector(out_pos.x, out_pos.y - 0.4 * inst.mod.height) mid2 = vector(self.input_bus[name].cx(), mid1.y) bus_pos = self.input_bus[name].center() self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos]) - # The pin is on M1, so we need another via as well - self.add_via_center(layers=self.m1_stack, - offset=out_pos) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer="m2", + offset=out_pos) diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index c07395f5..c261138a 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -140,21 +140,20 @@ class delay_chain(design.design): for load in self.load_inst_map[inv]: # Drop a via on each A pin a_pin = load.get_pin("A") - self.add_via_center(layers=self.m1_stack, - offset=a_pin.center()) - self.add_via_center(layers=self.m2_stack, - offset=a_pin.center()) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m3", + offset=a_pin.center()) # Route an M3 horizontal wire to the furthest z_pin = inv.get_pin("Z") a_pin = inv.get_pin("A") a_max = self.load_inst_map[inv][-1].get_pin("A") - self.add_via_center(layers=self.m1_stack, - offset=a_pin.center()) - self.add_via_center(layers=self.m1_stack, - offset=z_pin.center()) - self.add_via_center(layers=self.m2_stack, - offset=z_pin.center()) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=a_pin.center()) + self.add_via_stack_center(from_layer=z_pin.layer, + to_layer="m3", + offset=z_pin.center()) self.add_path("m3", [z_pin.center(), a_max.center()]) # Route Z to the A of the next stage @@ -191,8 +190,9 @@ class delay_chain(design.design): # input is A pin of first inverter a_pin = self.driver_inst_list[0].get_pin("A") - self.add_via_center(layers=self.m1_stack, - offset=a_pin.center()) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=a_pin.center()) self.add_layout_pin(text="in", layer="m2", offset=a_pin.ll().scale(1, 0), @@ -201,8 +201,9 @@ class delay_chain(design.design): # output is A pin of last load inverter last_driver_inst = self.driver_inst_list[-1] a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A") - self.add_via_center(layers=self.m1_stack, - offset=a_pin.center()) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=a_pin.center()) mid_point = vector(a_pin.cx() + 3 * self.m2_width, a_pin.cy()) self.add_path("m2", [a_pin.center(), mid_point, mid_point.scale(1, 0)]) self.add_layout_pin_segment_center(text="out", diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index cdc5ab92..52cbb2a1 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -457,7 +457,12 @@ class sram_1bank(sram_base): dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) self.add_wire(self.m2_stack[::-1], [src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()]) - # self.connect_hbus(src_pin, dest_pin) + self.add_via_stack_center(from_layer=src_pin.layer, + to_layer="m2", + offset=src_pin.center()) + self.add_via_stack_center(from_layer=dest_pin.layer, + to_layer="m2", + offset=dest_pin.center()) def route_row_addr_dff(self): """ Connect the output of the row flops to the bank pins """