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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 02:57:53 +02:00
Fix missing via LVS issues. LVS passing for some 20 tests.
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@@ -140,21 +140,20 @@ class delay_chain(design.design):
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for load in self.load_inst_map[inv]:
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# Drop a via on each A pin
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a_pin = load.get_pin("A")
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self.add_via_center(layers=self.m1_stack,
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offset=a_pin.center())
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self.add_via_center(layers=self.m2_stack,
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offset=a_pin.center())
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self.add_via_stack_center(from_layer=a_pin.layer,
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to_layer="m3",
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offset=a_pin.center())
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# Route an M3 horizontal wire to the furthest
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z_pin = inv.get_pin("Z")
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a_pin = inv.get_pin("A")
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a_max = self.load_inst_map[inv][-1].get_pin("A")
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self.add_via_center(layers=self.m1_stack,
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offset=a_pin.center())
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self.add_via_center(layers=self.m1_stack,
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offset=z_pin.center())
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self.add_via_center(layers=self.m2_stack,
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offset=z_pin.center())
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self.add_via_stack_center(from_layer=a_pin.layer,
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to_layer="m2",
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offset=a_pin.center())
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self.add_via_stack_center(from_layer=z_pin.layer,
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to_layer="m3",
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offset=z_pin.center())
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self.add_path("m3", [z_pin.center(), a_max.center()])
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# Route Z to the A of the next stage
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@@ -191,8 +190,9 @@ class delay_chain(design.design):
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# input is A pin of first inverter
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a_pin = self.driver_inst_list[0].get_pin("A")
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self.add_via_center(layers=self.m1_stack,
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offset=a_pin.center())
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self.add_via_stack_center(from_layer=a_pin.layer,
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to_layer="m2",
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offset=a_pin.center())
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self.add_layout_pin(text="in",
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layer="m2",
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offset=a_pin.ll().scale(1, 0),
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@@ -201,8 +201,9 @@ class delay_chain(design.design):
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# output is A pin of last load inverter
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last_driver_inst = self.driver_inst_list[-1]
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a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A")
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self.add_via_center(layers=self.m1_stack,
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offset=a_pin.center())
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self.add_via_stack_center(from_layer=a_pin.layer,
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to_layer="m2",
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offset=a_pin.center())
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mid_point = vector(a_pin.cx() + 3 * self.m2_width, a_pin.cy())
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self.add_path("m2", [a_pin.center(), mid_point, mid_point.scale(1, 0)])
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self.add_layout_pin_segment_center(text="out",
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