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Removed code for RW ports to not precharge on writes. Previously, the entire bitline was written where part was an old value and part was the wmask value.

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jsowash
2019-07-24 15:01:20 -07:00
parent 01493aab3e
commit 3bcb79d9d5
3 changed files with 13 additions and 18 deletions
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compiler/modules/control_logic.py
+8 -8
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@@ -628,14 +628,14 @@ class control_logic(design.design):
offset=out_pos)
def create_pen_row(self):
if self.port_type == "rw":
# input: gated_clk_bar, we_bar, output: pre_p_en
self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en",
mod=self.and2)
self.connect_inst(["gated_clk_buf", "we_bar", "pre_p_en", "vdd", "gnd"])
input_name = "pre_p_en"
else:
input_name = "gated_clk_buf"
# if self.port_type == "rw":
# # input: gated_clk_bar, we_bar, output: pre_p_en
# self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en",
# mod=self.and2)
# self.connect_inst(["gated_clk_buf", "we_bar", "pre_p_en", "vdd", "gnd"])
# input_name = "pre_p_en"
# else:
input_name = "gated_clk_buf"
# input: pre_p_en, output: p_en_bar
self.p_en_bar_inst=self.add_inst(name="inv_p_en_bar",