mirror of https://github.com/VLSIDA/OpenRAM.git
update gds library, generalize geometry reverse transform function
This commit is contained in:
parent
5b44dce50d
commit
3ab99d7f9c
|
|
@ -256,9 +256,9 @@ class instance(geometry):
|
||||||
new_pins.append(p)
|
new_pins.append(p)
|
||||||
return new_pins
|
return new_pins
|
||||||
|
|
||||||
def reverse_bitcell_transformation(self):
|
def reverse_transformation(self, cell_name):
|
||||||
path = []
|
path = []
|
||||||
bitcell_paths = []
|
cell_paths = []
|
||||||
pex_offsets = []
|
pex_offsets = []
|
||||||
Q_offsets = []
|
Q_offsets = []
|
||||||
Q_bar_offsets = []
|
Q_bar_offsets = []
|
||||||
|
|
@ -266,8 +266,9 @@ class instance(geometry):
|
||||||
def walk_subtree(node):
|
def walk_subtree(node):
|
||||||
path.append(node)
|
path.append(node)
|
||||||
|
|
||||||
if node.mod.name == 'pbitcell':
|
if node.mod.name == cell_name:
|
||||||
bitcell_paths.append(copy.copy(path))
|
print("bitcell found")
|
||||||
|
cell_paths.append(copy.copy(path))
|
||||||
|
|
||||||
Q_x = node.mod.get_normalized_storage_net_offset()[0][0]
|
Q_x = node.mod.get_normalized_storage_net_offset()[0][0]
|
||||||
Q_y = node.mod.get_normalized_storage_net_offset()[0][1]
|
Q_y = node.mod.get_normalized_storage_net_offset()[0][1]
|
||||||
|
|
@ -338,7 +339,7 @@ class instance(geometry):
|
||||||
return (uVector, vVector, origin)
|
return (uVector, vVector, origin)
|
||||||
|
|
||||||
walk_subtree(self)
|
walk_subtree(self)
|
||||||
for path in bitcell_paths:
|
for path in cell_paths:
|
||||||
vector_spaces = apply_path_transform(path)
|
vector_spaces = apply_path_transform(path)
|
||||||
origin = vector_spaces[2]
|
origin = vector_spaces[2]
|
||||||
pex_offsets.append([origin[0], origin[1]])
|
pex_offsets.append([origin[0], origin[1]])
|
||||||
|
|
|
||||||
|
|
@ -10,7 +10,7 @@ import debug
|
||||||
import design
|
import design
|
||||||
from globals import OPTS
|
from globals import OPTS
|
||||||
import logical_effort
|
import logical_effort
|
||||||
from tech import parameter, drc
|
from tech import parameter, drc, layer
|
||||||
|
|
||||||
|
|
||||||
class bitcell_base(design.design):
|
class bitcell_base(design.design):
|
||||||
|
|
@ -85,14 +85,15 @@ class bitcell_base(design.design):
|
||||||
Gets the location of the storage net labels to add top level
|
Gets the location of the storage net labels to add top level
|
||||||
labels for pex simulation.
|
labels for pex simulation.
|
||||||
"""
|
"""
|
||||||
#TODO: use getTexts to support custom bitcells
|
|
||||||
# If we generated the bitcell, we already know where Q and Q_bar are
|
# If we generated the bitcell, we already know where Q and Q_bar are
|
||||||
#if OPTS.bitcell is not "pbitcell":
|
if OPTS.bitcell is not "pbitcell":
|
||||||
# self.storage_net_offsets = []
|
self.storage_net_offsets = []
|
||||||
# for net in get_storage_net_names:
|
for i in range(0, len(self.get_storage_net_names())):
|
||||||
# if net is "Q" or "Q_bar":
|
for text in self.gds.getTexts(layer["metal1"]):
|
||||||
# for text in self.getTexts("metal1"):
|
if self.storage_nets[i] == text:
|
||||||
# self.storage_net_offsets.append(text.offsetInMicrons)
|
print(text)
|
||||||
|
|
||||||
|
|
||||||
return(self.storage_net_offsets)
|
return(self.storage_net_offsets)
|
||||||
|
|
||||||
def get_normalized_storage_net_offset(self):
|
def get_normalized_storage_net_offset(self):
|
||||||
|
|
@ -101,11 +102,11 @@ class bitcell_base(design.design):
|
||||||
of the bitcell. This is useful for making sense of offsets outside
|
of the bitcell. This is useful for making sense of offsets outside
|
||||||
of the bitcell.
|
of the bitcell.
|
||||||
"""
|
"""
|
||||||
|
print("get normalized")
|
||||||
Q_x = self.storage_net_offsets[0][0] - self.leftmost_xpos
|
Q_x = self.get_storage_net_offset()[0][0] - self.leftmost_xpos
|
||||||
Q_y = self.storage_net_offsets[0][1] - self.botmost_ypos
|
Q_y = self.get_storage_net_offset()[0][1] - self.botmost_ypos
|
||||||
Q_bar_x = self.storage_net_offsets[1][0] - self.leftmost_xpos
|
Q_bar_x = self.get_storage_net_offset()[1][0] - self.leftmost_xpos
|
||||||
Q_bar_y = self.storage_net_offsets[1][1] - self.botmost_ypos
|
Q_bar_y = self.get_storage_net_offset()[1][1] - self.botmost_ypos
|
||||||
|
|
||||||
normalized_storage_net_offset = [[Q_x,Q_y],[Q_bar_x,Q_bar_y]]
|
normalized_storage_net_offset = [[Q_x,Q_y],[Q_bar_x,Q_bar_y]]
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -94,21 +94,21 @@ class sram_base(design, verilog, lef):
|
||||||
# add pex labels for bitcell
|
# add pex labels for bitcell
|
||||||
for bank_num in range(0,len(self.bank_insts)):
|
for bank_num in range(0,len(self.bank_insts)):
|
||||||
bank = self.bank_insts[bank_num]
|
bank = self.bank_insts[bank_num]
|
||||||
pex_offsets = bank.reverse_bitcell_transformation()
|
pex_offsets = bank.reverse_transformation(bank.mod.bitcell.name)
|
||||||
|
|
||||||
bank_offset = pex_offsets[0] # offset bank relative to sram
|
bank_offset = pex_offsets[0] # offset bank relative to sram
|
||||||
Q_offset = pex_offsets[1] # offset of storage relative to bank
|
Q_offset = pex_offsets[1] # offset of storage relative to bank
|
||||||
Q_bar_offset = pex_offsets[2] # offset of storage relative to bank
|
Q_bar_offset = pex_offsets[2] # offset of storage relative to bank
|
||||||
|
|
||||||
layer = "metal1"
|
layer_name = "metal1"
|
||||||
|
|
||||||
for i in range(0,len(bank_offset)):
|
for i in range(0,len(bank_offset)):
|
||||||
|
|
||||||
Q = [bank_offset[i][0] + Q_offset[i][0], bank_offset[i][1] + Q_offset[i][1]]
|
Q = [bank_offset[i][0] + Q_offset[i][0], bank_offset[i][1] + Q_offset[i][1]]
|
||||||
Q_bar = [bank_offset[i][0] + Q_bar_offset[i][0], bank_offset[i][1] + Q_bar_offset[i][1]]
|
Q_bar = [bank_offset[i][0] + Q_bar_offset[i][0], bank_offset[i][1] + Q_bar_offset[i][1]]
|
||||||
|
|
||||||
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , layer, Q)
|
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , layer_name, Q)
|
||||||
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), layer, Q_bar)
|
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), layer_name, Q_bar)
|
||||||
|
|
||||||
# add pex labels for control logic
|
# add pex labels for control logic
|
||||||
for i in range (0,len(self.control_logic_insts)):
|
for i in range (0,len(self.control_logic_insts)):
|
||||||
|
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
||||||
magic
|
magic
|
||||||
tech scmos
|
tech scmos
|
||||||
timestamp 1577066121
|
timestamp 1577163318
|
||||||
<< nwell >>
|
<< nwell >>
|
||||||
rect -8 35 42 57
|
rect -8 35 42 57
|
||||||
<< pwell >>
|
<< pwell >>
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue