diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 1c037fdf..46a7bd6e 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -256,18 +256,19 @@ class instance(geometry): new_pins.append(p) return new_pins - def reverse_bitcell_transformation(self): + def reverse_transformation(self, cell_name): path = [] - bitcell_paths = [] + cell_paths = [] pex_offsets = [] Q_offsets = [] Q_bar_offsets = [] def walk_subtree(node): path.append(node) - - if node.mod.name == 'pbitcell': - bitcell_paths.append(copy.copy(path)) + + if node.mod.name == cell_name: + print("bitcell found") + cell_paths.append(copy.copy(path)) Q_x = node.mod.get_normalized_storage_net_offset()[0][0] Q_y = node.mod.get_normalized_storage_net_offset()[0][1] @@ -338,7 +339,7 @@ class instance(geometry): return (uVector, vVector, origin) walk_subtree(self) - for path in bitcell_paths: + for path in cell_paths: vector_spaces = apply_path_transform(path) origin = vector_spaces[2] pex_offsets.append([origin[0], origin[1]]) diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index ea394548..3661abf7 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -10,7 +10,7 @@ import debug import design from globals import OPTS import logical_effort -from tech import parameter, drc +from tech import parameter, drc, layer class bitcell_base(design.design): @@ -85,14 +85,15 @@ class bitcell_base(design.design): Gets the location of the storage net labels to add top level labels for pex simulation. """ - #TODO: use getTexts to support custom bitcells # If we generated the bitcell, we already know where Q and Q_bar are - #if OPTS.bitcell is not "pbitcell": - # self.storage_net_offsets = [] - # for net in get_storage_net_names: - # if net is "Q" or "Q_bar": - # for text in self.getTexts("metal1"): - # self.storage_net_offsets.append(text.offsetInMicrons) + if OPTS.bitcell is not "pbitcell": + self.storage_net_offsets = [] + for i in range(0, len(self.get_storage_net_names())): + for text in self.gds.getTexts(layer["metal1"]): + if self.storage_nets[i] == text: + print(text) + + return(self.storage_net_offsets) def get_normalized_storage_net_offset(self): @@ -101,11 +102,11 @@ class bitcell_base(design.design): of the bitcell. This is useful for making sense of offsets outside of the bitcell. """ - - Q_x = self.storage_net_offsets[0][0] - self.leftmost_xpos - Q_y = self.storage_net_offsets[0][1] - self.botmost_ypos - Q_bar_x = self.storage_net_offsets[1][0] - self.leftmost_xpos - Q_bar_y = self.storage_net_offsets[1][1] - self.botmost_ypos + print("get normalized") + Q_x = self.get_storage_net_offset()[0][0] - self.leftmost_xpos + Q_y = self.get_storage_net_offset()[0][1] - self.botmost_ypos + Q_bar_x = self.get_storage_net_offset()[1][0] - self.leftmost_xpos + Q_bar_y = self.get_storage_net_offset()[1][1] - self.botmost_ypos normalized_storage_net_offset = [[Q_x,Q_y],[Q_bar_x,Q_bar_y]] diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index cd9fb19d..6a7e996e 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -94,21 +94,21 @@ class sram_base(design, verilog, lef): # add pex labels for bitcell for bank_num in range(0,len(self.bank_insts)): bank = self.bank_insts[bank_num] - pex_offsets = bank.reverse_bitcell_transformation() + pex_offsets = bank.reverse_transformation(bank.mod.bitcell.name) bank_offset = pex_offsets[0] # offset bank relative to sram Q_offset = pex_offsets[1] # offset of storage relative to bank Q_bar_offset = pex_offsets[2] # offset of storage relative to bank - layer = "metal1" + layer_name = "metal1" for i in range(0,len(bank_offset)): Q = [bank_offset[i][0] + Q_offset[i][0], bank_offset[i][1] + Q_offset[i][1]] Q_bar = [bank_offset[i][0] + Q_bar_offset[i][0], bank_offset[i][1] + Q_bar_offset[i][1]] - self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , layer, Q) - self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), layer, Q_bar) + self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , layer_name, Q) + self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), layer_name, Q_bar) # add pex labels for control logic for i in range (0,len(self.control_logic_insts)): diff --git a/technology/scn4m_subm/gds_lib/cell_6t.gds b/technology/scn4m_subm/gds_lib/cell_6t.gds index 14d6ab7e..6bfc4431 100644 Binary files a/technology/scn4m_subm/gds_lib/cell_6t.gds and b/technology/scn4m_subm/gds_lib/cell_6t.gds differ diff --git a/technology/scn4m_subm/gds_lib/dff.gds b/technology/scn4m_subm/gds_lib/dff.gds index 7825c3bc..ca6d2b6d 100644 Binary files a/technology/scn4m_subm/gds_lib/dff.gds and b/technology/scn4m_subm/gds_lib/dff.gds differ diff --git a/technology/scn4m_subm/gds_lib/replica_cell_6t.gds b/technology/scn4m_subm/gds_lib/replica_cell_6t.gds index 191f1206..30f5a37e 100644 Binary files a/technology/scn4m_subm/gds_lib/replica_cell_6t.gds and b/technology/scn4m_subm/gds_lib/replica_cell_6t.gds differ diff --git a/technology/scn4m_subm/gds_lib/sense_amp.gds b/technology/scn4m_subm/gds_lib/sense_amp.gds index cf5fa587..5ffbb0d5 100644 Binary files a/technology/scn4m_subm/gds_lib/sense_amp.gds and b/technology/scn4m_subm/gds_lib/sense_amp.gds differ diff --git a/technology/scn4m_subm/gds_lib/tri_gate.gds b/technology/scn4m_subm/gds_lib/tri_gate.gds index ad83f4c6..088e8870 100644 Binary files a/technology/scn4m_subm/gds_lib/tri_gate.gds and b/technology/scn4m_subm/gds_lib/tri_gate.gds differ diff --git a/technology/scn4m_subm/gds_lib/write_driver.gds b/technology/scn4m_subm/gds_lib/write_driver.gds index 8223c795..9e201f24 100644 Binary files a/technology/scn4m_subm/gds_lib/write_driver.gds and b/technology/scn4m_subm/gds_lib/write_driver.gds differ diff --git a/technology/scn4m_subm/mag_lib/cell_6t.mag b/technology/scn4m_subm/mag_lib/cell_6t.mag index 17206ac6..e8c16eff 100644 --- a/technology/scn4m_subm/mag_lib/cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/cell_6t.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1577066121 +timestamp 1577163318 << nwell >> rect -8 35 42 57 << pwell >>