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This commit is contained in:
mrg 2020-08-17 14:35:39 -07:00
parent 60224b105f
commit 3a692e2846
1 changed files with 3 additions and 2 deletions
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5
compiler/base/design.py
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@ -230,13 +230,14 @@ class design(hierarchy_design):
self.write_ports = [] self.write_ports = []
# These are the write-only port indices. # These are the write-only port indices.
self.writeonly_ports = [] self.writeonly_ports = []
# These are teh read/write and read-only port indice # These are the read/write and read-only port indices
self.read_ports = [] self.read_ports = []
# These are the read-only port indices. # These are the read-only port indices.
self.readonly_ports = [] self.readonly_ports = []
# These are all the ports # These are all the ports
self.all_ports = list(range(total_ports)) self.all_ports = list(range(total_ports))
# The order is always fixed as RW, W, R
port_number = 0 port_number = 0
for port in range(OPTS.num_rw_ports): for port in range(OPTS.num_rw_ports):
self.readwrite_ports.append(port_number) self.readwrite_ports.append(port_number)