From 3a692e28469ef130f8c58440422ac8faf4275d74 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 17 Aug 2020 14:35:39 -0700 Subject: [PATCH] Comment updates --- compiler/base/design.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/base/design.py b/compiler/base/design.py index 2a79120d..ee985fec 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -230,13 +230,14 @@ class design(hierarchy_design): self.write_ports = [] # These are the write-only port indices. self.writeonly_ports = [] - # These are teh read/write and read-only port indice + # These are the read/write and read-only port indices self.read_ports = [] # These are the read-only port indices. self.readonly_ports = [] # These are all the ports self.all_ports = list(range(total_ports)) - + + # The order is always fixed as RW, W, R port_number = 0 for port in range(OPTS.num_rw_ports): self.readwrite_ports.append(port_number)