mirror of https://github.com/VLSIDA/OpenRAM.git
add simple sram sizing for netlist only
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parent
18573c0e42
commit
3a06141030
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@ -96,8 +96,10 @@ def get_libcell_size(name, units, lpp):
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Open a GDS file and return the library cell size from either the
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Open a GDS file and return the library cell size from either the
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bounding box or a border layer.
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bounding box or a border layer.
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"""
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"""
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cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
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if not OPTS.netlist_only:
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return(get_gds_size(name, cell_gds, units, lpp))
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cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
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return(get_gds_size(name, cell_gds, units, lpp))
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return (0,0,)
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def get_gds_pins(pin_names, name, gds_filename, units):
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def get_gds_pins(pin_names, name, gds_filename, units):
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@ -128,8 +130,11 @@ def get_libcell_pins(pin_list, name, units):
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Open a GDS file and find the pins in pin_list as text on a given layer.
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Open a GDS file and find the pins in pin_list as text on a given layer.
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Return these as a rectangle layer pair for each pin.
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Return these as a rectangle layer pair for each pin.
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"""
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"""
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cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
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if not OPTS.netlist_only:
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return(get_gds_pins(pin_list, name, cell_gds, units))
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cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
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return(get_gds_pins(pin_list, name, cell_gds, units))
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else:
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return
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@ -57,6 +57,7 @@ class bank(design.design):
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def create_netlist(self):
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def create_netlist(self):
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self.compute_sizes()
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self.compute_sizes()
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self.add_modules()
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self.add_modules()
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self.add_pins() # Must create the replica bitcell array first
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self.add_pins() # Must create the replica bitcell array first
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@ -23,8 +23,11 @@ class sram_config:
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# This will get over-written when we determine the organization
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# This will get over-written when we determine the organization
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self.words_per_row = words_per_row
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self.words_per_row = words_per_row
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if not OPTS.netlist_only:
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self.compute_sizes()
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else:
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self.compute_simple_sram_sizes()
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self.compute_sizes()
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def set_local_config(self, module):
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def set_local_config(self, module):
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@ -35,6 +38,14 @@ class sram_config:
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# Copy all the variables to the local module
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# Copy all the variables to the local module
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for member in members:
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for member in members:
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setattr(module,member,getattr(self,member))
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setattr(module,member,getattr(self,member))
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def compute_simple_sram_sizes(self):
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self.row_addr_size = int(log(OPTS.num_words, 2))
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self.col_addr_size = int(log(OPTS.word_size, 2))
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self.words_per_row = 1
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self.num_rows = OPTS.num_words
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self.num_cols = OPTS.word_size
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self.bank_addr_size = self.col_addr_size + self.row_addr_size
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self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
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def compute_sizes(self):
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def compute_sizes(self):
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""" Computes the organization of the memory using bitcell size by trying to make it square."""
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""" Computes the organization of the memory using bitcell size by trying to make it square."""
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