diff --git a/compiler/modules/bitcell.py b/compiler/modules/bitcell.py
index 2f8a843c..8e8a9a35 100644
--- a/compiler/modules/bitcell.py
+++ b/compiler/modules/bitcell.py
@@ -48,15 +48,44 @@ class bitcell(design.design):
     
     def list_row_pins(self):
         # Creates a list of row pins
-        row_pins = ["WL"]    
+        row_pins = ["wl"]    
+        return row_pins
+    
+    def list_read_row_pins(self):
+        # Creates a list of row pins
+        row_pins = ["wl"]    
+        return row_pins
+        
+    def list_write_row_pins(self):
+        # Creates a list of row pins
+        row_pins = ["wl"]    
         return row_pins
     
     
     def list_column_pins(self):
         # Creates a list of column pins
-        column_pins = ["BL", "BR"]
+        column_pins = ["bl", "br"]
         return column_pins
         
+    def list_read_column_pins(self):
+        # Creates a list of column pins
+        column_pins = ["bl"]
+        return column_pins
+    
+    def list_read_bar_column_pins(self):
+        # Creates a list of column pins
+        column_pins = ["br"]
+        return column_pins
+        
+    def list_write_column_pins(self):
+        # Creates a list of column pins
+        column_pins = ["bl"]
+        return column_pins
+    
+    def list_write_bar_column_pins(self):
+        # Creates a list of column pins
+        column_pins = ["br"]
+        return column_pins
     
     def analytical_power(self, proc, vdd, temp, load):
         """Bitcell power in nW. Only characterizes leakage."""
diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py
index 5fac6c06..dc77e5d1 100644
--- a/compiler/tests/05_pbitcell_array_test.py
+++ b/compiler/tests/05_pbitcell_array_test.py
@@ -24,12 +24,16 @@ class array_multiport_test(openram_test):
         import bitcell_array
 
         OPTS.bitcell = "pbitcell"
+        OPTS.rw_ports = 2
+        OPTS.r_ports = 2
+        OPTS.w_ports = 2
+        
         debug.info(2, "Testing 4x4 array for multiport bitcell")
         a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
         self.local_check(a)
 
         OPTS.check_lvsdrc = True
-        globals.end_openram()
+        #globals.end_openram()
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":