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Remove setup/hold measure and compute it directly.

This commit is contained in:
mrg 2021-05-14 10:11:14 -07:00
parent 9555b52aaa
commit 3959cf73d1
1 changed files with 6 additions and 6 deletions
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12
compiler/characterizer/setup_hold.py
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@ -170,11 +170,11 @@ class setup_hold():
self.stim.run_sim(self.stim_sp) self.stim.run_sim(self.stim_sp)
ideal_clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay")) ideal_clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
# We use a 1/2 speed clock for some reason... # We use a 1/2 speed clock for some reason...
setuphold_time = (feasible_bound - 2 * self.period) / 1e9 setuphold_time = (feasible_bound - 2 * self.period)
if mode == "SETUP": # SETUP is clk-din, not din-clk if mode == "SETUP": # SETUP is clk-din, not din-clk
passing_setuphold_time = -1e9 * setuphold_time passing_setuphold_time = -1 * setuphold_time
else: else:
passing_setuphold_time = 1e9 * setuphold_time passing_setuphold_time = setuphold_time
debug.info(2, "*** {0} CHECK: {1} Ideal Clk-to-Q: {2} Setup/Hold: {3}".format(mode, debug.info(2, "*** {0} CHECK: {1} Ideal Clk-to-Q: {2} Setup/Hold: {3}".format(mode,
correct_value, correct_value,
ideal_clk_to_q, ideal_clk_to_q,
@ -208,11 +208,11 @@ class setup_hold():
self.stim.run_sim(self.stim_sp) self.stim.run_sim(self.stim_sp)
clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay")) clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
# We use a 1/2 speed clock for some reason... # We use a 1/2 speed clock for some reason...
setuphold_time = (target_time - 2 * self.period) / 1e9 setuphold_time = (target_time - 2 * self.period)
if mode == "SETUP": # SETUP is clk-din, not din-clk if mode == "SETUP": # SETUP is clk-din, not din-clk
passing_setuphold_time = -1e9 * setuphold_time passing_setuphold_time = -1 * setuphold_time
else: else:
passing_setuphold_time = 1e9 * setuphold_time passing_setuphold_time = setuphold_time
if type(clk_to_q) == float and (clk_to_q < 1.1 * ideal_clk_to_q): if type(clk_to_q) == float and (clk_to_q < 1.1 * ideal_clk_to_q):
debug.info(2, "PASS Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time)) debug.info(2, "PASS Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time))
feasible_bound = target_time feasible_bound = target_time