From 3820861ce8433e83a8b2882278c30d90ea664e10 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 7 Feb 2018 13:10:45 -0800 Subject: [PATCH] Increase control delay line from 4 inverters to 3 FO4 delays. Need to dynamically adjust this. --- compiler/replica_bitline.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/replica_bitline.py b/compiler/replica_bitline.py index fb8ede4c..d90277b6 100644 --- a/compiler/replica_bitline.py +++ b/compiler/replica_bitline.py @@ -81,7 +81,7 @@ class replica_bitline(design.design): self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.rows) self.add_mod(self.rbl) - self.delay_chain = self.mod_delay_chain([1, 1, 1]) + self.delay_chain = self.mod_delay_chain([4, 4, 4]) self.add_mod(self.delay_chain) self.inv = pinv()