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Add multiple control logic port types.

This commit is contained in:
mrg 2019-07-15 17:07:50 -07:00
parent e550d6ff10
commit 37c15937e2
1 changed files with 9 additions and 2 deletions
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11
compiler/tests/16_control_logic_test.py
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@ -22,11 +22,18 @@ class control_logic_test(openram_test):
import control_logic import control_logic
import tech import tech
# check control logic for single port debug.info(1, "Testing sample for control_logic_rw")
debug.info(1, "Testing sample for control_logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32) a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32)
self.local_check(a) self.local_check(a)
debug.info(1, "Testing sample for control_logic_r")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32, port_type="r")
self.local_check(a)
debug.info(1, "Testing sample for control_logic_w")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32, port_type="w")
self.local_check(a)
# run the test from the command line # run the test from the command line
if __name__ == "__main__": if __name__ == "__main__":
(OPTS, args) = globals.parse_args() (OPTS, args) = globals.parse_args()