From 37c15937e21d3290f00f7f9c02c69ab63b33aba2 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jul 2019 17:07:50 -0700 Subject: [PATCH] Add multiple control logic port types. --- compiler/tests/16_control_logic_test.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 13e6c46c..f8fa3061 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -22,10 +22,17 @@ class control_logic_test(openram_test): import control_logic import tech - # check control logic for single port - debug.info(1, "Testing sample for control_logic") + debug.info(1, "Testing sample for control_logic_rw") a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32) self.local_check(a) + + debug.info(1, "Testing sample for control_logic_r") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32, port_type="r") + self.local_check(a) + + debug.info(1, "Testing sample for control_logic_w") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32, port_type="w") + self.local_check(a) # run the test from the command line if __name__ == "__main__":