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Remove another boundary subcell

This commit is contained in:
mrg 2020-10-08 16:58:19 -07:00
parent 8d5db50062
commit 3648401e67
1 changed files with 4 additions and 8 deletions
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10
compiler/custom/s8_row_end.py
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@ -9,16 +9,14 @@
import debug import debug
import design import design
import utils import utils
from globals import OPTS from tech import layer, GDS
from tech import parameter, drc, layer, GDS
class s8_row_end(design.design): class s8_row_end(design.design):
def __init__(self, version, name=""): def __init__(self, version, name=""):
super().__init__(name) super().__init__(name)
pin_names = ["wl", "vpwr"] pin_names = ["wl", "vpwr"]
type_list = ["OUTPUT", "POWER"]
if version == "rowend": if version == "rowend":
self.name = "s8sram16x16_rowend" self.name = "s8sram16x16_rowend"
@ -29,10 +27,8 @@ class s8_row_end(design.design):
design.design.__init__(self, name=self.name) design.design.__init__(self, name=self.name)
(self.width, self.height) = utils.get_libcell_size(self.name, (self.width, self.height) = utils.get_libcell_size(self.name,
GDS["unit"], GDS["unit"],
layer["mem"], layer["mem"])
"s8sram16x16_rowend_ce\x00")
self.pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"]) self.pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
self.add_pin("wl", "OUTPUT") self.add_pin("wl", "OUTPUT")
self.add_pin("vpwr", "POWER") self.add_pin("vpwr", "POWER")