mirror of https://github.com/VLSIDA/OpenRAM.git
update freepdk bitcell for pex
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.SUBCKT cell_6t bl br wl vdd gnd
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.SUBCKT cell_6t bl br wl vdd gnd
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* Inverter 1
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* Inverter 1
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MM0 Qbar Q gnd gnd NMOS_VTG W=205.00n L=50n
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MM0 Q_bar Q gnd gnd NMOS_VTG W=205.00n L=50n
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MM4 Qbar Q vdd vdd PMOS_VTG W=90n L=50n
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MM4 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n
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* Inverer 2
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* Inverer 2
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MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n
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MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n
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