luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/dev' into dev

This commit is contained in:
Jesse Cirimelli-Low 2021-06-21 15:27:32 -07:00
parent 2760beae34 bb1ac1a38e
commit 3502bec231
2 changed files with 16 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
compiler/sram/sram_base.py
View File

@ -15,7 +15,7 @@ from design import design
from verilog import verilog from verilog import verilog
from lef import lef from lef import lef
from sram_factory import factory from sram_factory import factory
from tech import spice, layer from tech import spice
class sram_base(design, verilog, lef): class sram_base(design, verilog, lef):
@ -553,13 +553,13 @@ class sram_base(design, verilog, lef):
temp.append("rbl_bl{0}".format(port)) temp.append("rbl_bl{0}".format(port))
for port in self.write_ports: for port in self.write_ports:
for bit in range(self.word_size + self.num_spare_cols): for bit in range(self.word_size + self.num_spare_cols):
temp.append("bank_din{0}[{1}]".format(port, bit)) temp.append("bank_din{0}_{1}".format(port, bit))
for port in self.all_ports: for port in self.all_ports:
for bit in range(self.bank_addr_size): for bit in range(self.bank_addr_size):
temp.append("a{0}[{1}]".format(port, bit)) temp.append("a{0}_{1}".format(port, bit))
if(self.num_banks > 1): if(self.num_banks > 1):
for port in self.all_ports: for port in self.all_ports:
temp.append("bank_sel{0}[{1}]".format(port, bank_num)) temp.append("bank_sel{0}_{1}".format(port, bank_num))
for port in self.read_ports: for port in self.read_ports:
temp.append("s_en{0}".format(port)) temp.append("s_en{0}".format(port))
for port in self.all_ports: for port in self.all_ports:
@ -567,12 +567,9 @@ class sram_base(design, verilog, lef):
for port in self.write_ports: for port in self.write_ports:
temp.append("w_en{0}".format(port)) temp.append("w_en{0}".format(port))
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
temp.append("bank_wmask{}[{}]".format(port, bit)) temp.append("bank_wmask{0}_{1}".format(port, bit))
if self.num_spare_cols == 1: for bit in range(self.num_spare_cols):
temp.append("bank_spare_wen{0}".format(port)) temp.append("bank_spare_wen{0}_{1}".format(port, bit))
else:
for bit in range(self.num_spare_cols):
temp.append("bank_spare_wen{0}_{1}".format(port, bit))
for port in self.all_ports: for port in self.all_ports:
temp.append("wl_en{0}".format(port)) temp.append("wl_en{0}".format(port))
temp.extend(self.ext_supplies) temp.extend(self.ext_supplies)
@ -622,7 +619,7 @@ class sram_base(design, verilog, lef):
outputs = [] outputs = []
for bit in range(self.row_addr_size): for bit in range(self.row_addr_size):
inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size)) inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size))
outputs.append("a{}[{}]".format(port, bit + self.col_addr_size)) outputs.append("a{}_{}".format(port, bit + self.col_addr_size))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
@ -640,7 +637,7 @@ class sram_base(design, verilog, lef):
outputs = [] outputs = []
for bit in range(self.col_addr_size): for bit in range(self.col_addr_size):
inputs.append("addr{}[{}]".format(port, bit)) inputs.append("addr{}[{}]".format(port, bit))
outputs.append("a{}[{}]".format(port, bit)) outputs.append("a{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
@ -662,7 +659,7 @@ class sram_base(design, verilog, lef):
outputs = [] outputs = []
for bit in range(self.word_size + self.num_spare_cols): for bit in range(self.word_size + self.num_spare_cols):
inputs.append("din{}[{}]".format(port, bit)) inputs.append("din{}[{}]".format(port, bit))
outputs.append("bank_din{}[{}]".format(port, bit)) outputs.append("bank_din{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
@ -684,7 +681,7 @@ class sram_base(design, verilog, lef):
outputs = [] outputs = []
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
inputs.append("wmask{}[{}]".format(port, bit)) inputs.append("wmask{}[{}]".format(port, bit))
outputs.append("bank_wmask{}[{}]".format(port, bit)) outputs.append("bank_wmask{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
@ -709,7 +706,7 @@ class sram_base(design, verilog, lef):
outputs.append("bank_spare_wen{}".format(port)) outputs.append("bank_spare_wen{}".format(port))
else: else:
for bit in range(self.num_spare_cols): for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}_{}]".format(port, bit)) inputs.append("spare_wen{}[{}]".format(port, bit))
outputs.append("bank_spare_wen{}_{}".format(port, bit)) outputs.append("bank_spare_wen{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)

1
compiler/sram/sram_config.py
View File

@ -99,7 +99,6 @@ class sram_config:
+ " Bank addr size: {}".format(self.bank_addr_size)) + " Bank addr size: {}".format(self.bank_addr_size))
num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
print(num_ports)
if num_ports == 1: if num_ports == 1:
if ((self.num_cols + num_ports + self.num_spare_cols) % array_col_multiple != 0): if ((self.num_cols + num_ports + self.num_spare_cols) % array_col_multiple != 0):
debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, array_col_multiple), -1) debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, array_col_multiple), -1)