diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py
index 553cf3a6..0b8eac44 100644
--- a/compiler/sram/sram_base.py
+++ b/compiler/sram/sram_base.py
@@ -15,7 +15,7 @@ from design import design
 from verilog import verilog
 from lef import lef
 from sram_factory import factory
-from tech import spice, layer
+from tech import spice
 
 
 class sram_base(design, verilog, lef):
@@ -553,13 +553,13 @@ class sram_base(design, verilog, lef):
             temp.append("rbl_bl{0}".format(port))
         for port in self.write_ports:
             for bit in range(self.word_size + self.num_spare_cols):
-                temp.append("bank_din{0}[{1}]".format(port, bit))
+                temp.append("bank_din{0}_{1}".format(port, bit))
         for port in self.all_ports:
             for bit in range(self.bank_addr_size):
-                temp.append("a{0}[{1}]".format(port, bit))
+                temp.append("a{0}_{1}".format(port, bit))
         if(self.num_banks > 1):
             for port in self.all_ports:
-                temp.append("bank_sel{0}[{1}]".format(port, bank_num))
+                temp.append("bank_sel{0}_{1}".format(port, bank_num))
         for port in self.read_ports:
             temp.append("s_en{0}".format(port))
         for port in self.all_ports:
@@ -567,12 +567,9 @@ class sram_base(design, verilog, lef):
         for port in self.write_ports:
             temp.append("w_en{0}".format(port))
             for bit in range(self.num_wmasks):
-                temp.append("bank_wmask{}[{}]".format(port, bit))
-            if self.num_spare_cols == 1:
-                temp.append("bank_spare_wen{0}".format(port))
-            else:
-                for bit in range(self.num_spare_cols):
-                    temp.append("bank_spare_wen{0}_{1}".format(port, bit))
+                temp.append("bank_wmask{0}_{1}".format(port, bit))
+            for bit in range(self.num_spare_cols):
+                temp.append("bank_spare_wen{0}_{1}".format(port, bit))
         for port in self.all_ports:
             temp.append("wl_en{0}".format(port))
         temp.extend(self.ext_supplies)
@@ -622,7 +619,7 @@ class sram_base(design, verilog, lef):
             outputs = []
             for bit in range(self.row_addr_size):
                 inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size))
-                outputs.append("a{}[{}]".format(port, bit + self.col_addr_size))
+                outputs.append("a{}_{}".format(port, bit + self.col_addr_size))
 
             self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
 
@@ -640,7 +637,7 @@ class sram_base(design, verilog, lef):
             outputs = []
             for bit in range(self.col_addr_size):
                 inputs.append("addr{}[{}]".format(port, bit))
-                outputs.append("a{}[{}]".format(port, bit))
+                outputs.append("a{}_{}".format(port, bit))
 
             self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
 
@@ -662,7 +659,7 @@ class sram_base(design, verilog, lef):
             outputs = []
             for bit in range(self.word_size + self.num_spare_cols):
                 inputs.append("din{}[{}]".format(port, bit))
-                outputs.append("bank_din{}[{}]".format(port, bit))
+                outputs.append("bank_din{}_{}".format(port, bit))
 
             self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
 
@@ -684,7 +681,7 @@ class sram_base(design, verilog, lef):
             outputs = []
             for bit in range(self.num_wmasks):
                 inputs.append("wmask{}[{}]".format(port, bit))
-                outputs.append("bank_wmask{}[{}]".format(port, bit))
+                outputs.append("bank_wmask{}_{}".format(port, bit))
 
             self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
 
@@ -709,7 +706,7 @@ class sram_base(design, verilog, lef):
                 outputs.append("bank_spare_wen{}".format(port))
             else:
                 for bit in range(self.num_spare_cols):
-                    inputs.append("spare_wen{}_{}]".format(port, bit))
+                    inputs.append("spare_wen{}[{}]".format(port, bit))
                     outputs.append("bank_spare_wen{}_{}".format(port, bit))
 
             self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py
index 35226932..0916d0f4 100644
--- a/compiler/sram/sram_config.py
+++ b/compiler/sram/sram_config.py
@@ -48,7 +48,7 @@ class sram_config:
 
         self.num_words_per_bank = self.num_words / self.num_banks
         self.num_bits_per_bank = self.word_size * self.num_words_per_bank
-        
+
         # If this was hard coded, don't dynamically compute it!
         if not self.words_per_row:
             # Compute the area of the bitcells and estimate a square bank (excluding auxiliary circuitry)
@@ -65,11 +65,11 @@ class sram_config:
 
         self.recompute_sizes()
 
-        # Set word_per_row in OPTS 
+        # Set word_per_row in OPTS
         OPTS.words_per_row = self.words_per_row
         debug.info(1, "Set SRAM Words Per Row={}".format(OPTS.words_per_row))
 
-        
+
     def recompute_sizes(self):
         """
         Calculate the auxiliary values assuming fixed number of words per row.
@@ -99,14 +99,13 @@ class sram_config:
                    + " Bank addr size: {}".format(self.bank_addr_size))
 
         num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
-        print(num_ports)
         if num_ports == 1:
             if ((self.num_cols + num_ports + self.num_spare_cols) % array_col_multiple != 0):
                 debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, array_col_multiple), -1)
 
             if ((self.num_rows + num_ports) % array_row_multiple != 0):
                 debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.num_rows + num_ports, array_row_multiple), -1)
-                
+
     def estimate_words_per_row(self, tentative_num_cols, word_size):
         """
         This provides a heuristic rounded estimate for the number of words