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remove debug print statements
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@@ -68,8 +68,6 @@ class dummy_array(bitcell_base_array):
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core_block[(0 + r) % 2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
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core_block[(1 + r) % 2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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print(core_block)
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#print(r, c)
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#print(core_block)
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