mirror of https://github.com/VLSIDA/OpenRAM.git
Remove used gated_clk instead of cs for read-only control logic.
This commit is contained in:
Matt Guthaus
parent
3c4d559308
commit
33a7683473
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@ -173,8 +173,9 @@ class control_logic(design.design):
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self.create_wlen_row()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.create_wen_row()
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if (self.port_type == "rw") or (self.port_type == "r"):
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if self.port_type == "rw":
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self.create_rbl_in_row()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.create_pen_row()
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self.create_sen_row()
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self.create_rbl()
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@ -207,9 +208,10 @@ class control_logic(design.design):
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height = self.w_en_inst.uy()
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control_center_y = self.w_en_inst.uy()
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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if self.port_type == "rw":
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self.place_rbl_in_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.place_pen_row(row)
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row += 1
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self.place_sen_row(row)
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@ -248,9 +250,13 @@ class control_logic(design.design):
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def create_rbl(self):
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""" Create the replica bitline """
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if self.port_type == "r":
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input_name = "gated_clk_bar"
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else:
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input_name = "rbl_in"
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self.rbl_inst=self.add_inst(name="replica_bitline",
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mod=self.replica_bitline)
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self.connect_inst(["rbl_in", "pre_s_en", "vdd", "gnd"])
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self.connect_inst([input_name, "pre_s_en", "vdd", "gnd"])
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def place_rbl(self,row):
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""" Place the replica bitline """
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@ -394,15 +400,10 @@ class control_logic(design.design):
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def create_rbl_in_row(self):
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if self.port_type == "rw":
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input_name = "we_bar"
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else:
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input_name = "cs_bar"
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# input: gated_clk_bar, we_bar, output: rbl_in
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self.rbl_in_inst=self.add_inst(name="and2_rbl_in",
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mod=self.and2)
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self.connect_inst(["gated_clk_bar", input_name, "rbl_in", "vdd", "gnd"])
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self.connect_inst(["gated_clk_bar", "we_bar", "rbl_in", "vdd", "gnd"])
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def place_rbl_in_row(self,row):
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x_off = self.control_x_offset
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@ -418,15 +419,16 @@ class control_logic(design.design):
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if self.port_type == "rw":
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input_name = "we_bar"
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else:
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input_name = "cs_bar"
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# Connect the NAND gate inputs to the bus
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rbl_in_map = zip(["A", "B"], ["gated_clk_bar", "we_bar"])
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self.connect_vertical_bus(rbl_in_map, self.rbl_in_inst, self.rail_offsets)
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# Connect the NAND gate inputs to the bus
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rbl_in_map = zip(["A", "B"], ["gated_clk_bar", input_name])
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self.connect_vertical_bus(rbl_in_map, self.rbl_in_inst, self.rail_offsets)
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# Connect the output of the precharge enable to the RBL input
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out_pos = self.rbl_in_inst.get_pin("Z").center()
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if self.port_type == "rw":
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out_pos = self.rbl_in_inst.get_pin("Z").center()
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else:
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out_pos = vector(self.rail_offsets["gated_clk_bar"].x, self.rbl_inst.by()-3*self.m2_pitch)
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in_pos = self.rbl_inst.get_pin("en").center()
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mid1 = vector(in_pos.x,out_pos.y)
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self.add_wire(("metal3","via2","metal2"),[out_pos, mid1, in_pos])
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@ -439,51 +441,48 @@ class control_logic(design.design):
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def create_pen_row(self):
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if self.port_type == "rw":
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input_name = "we_bar"
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# input: gated_clk_bar, we_bar, output: pre_p_en
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self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en",
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mod=self.and2)
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self.connect_inst(["gated_clk_buf", "we_bar", "pre_p_en", "vdd", "gnd"])
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input_name = "pre_p_en"
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else:
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# No we for read-only reports, so use cs
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input_name = "cs_bar"
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# input: gated_clk_bar, we_bar, output: pre_p_en
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self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en",
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mod=self.and2)
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self.connect_inst(["gated_clk_buf", input_name, "pre_p_en", "vdd", "gnd"])
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input_name = "gated_clk_buf"
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# input: pre_p_en, output: p_en_bar
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self.p_en_bar_inst=self.add_inst(name="inv_p_en_bar",
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mod=self.inv8)
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self.connect_inst(["pre_p_en", "p_en_bar", "vdd", "gnd"])
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self.connect_inst([input_name, "p_en_bar", "vdd", "gnd"])
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def place_pen_row(self,row):
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x_off = self.control_x_offset
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(y_off,mirror)=self.get_offset(row)
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offset = vector(x_off, y_off)
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self.pre_p_en_inst.place(offset, mirror)
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if self.port_type == "rw":
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offset = vector(x_off, y_off)
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self.pre_p_en_inst.place(offset, mirror)
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x_off += self.and2.width
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x_off += self.and2.width
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offset = vector(x_off,y_off)
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self.p_en_bar_inst.place(offset, mirror)
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self.row_end_inst.append(self.pre_p_en_inst)
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self.row_end_inst.append(self.p_en_bar_inst)
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def route_pen(self):
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if self.port_type == "rw":
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input_name = "we_bar"
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# Connect the NAND gate inputs to the bus
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pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", "we_bar"])
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self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets)
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out_pos = self.pre_p_en_inst.get_pin("Z").center()
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in_pos = self.p_en_bar_inst.get_pin("A").lc()
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mid1 = vector(out_pos.x,in_pos.y)
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self.add_wire(("metal1","via1","metal2"),[out_pos,mid1,in_pos])
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else:
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# No we for read-only reports, so use cs
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input_name = "cs_bar"
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# Connect the NAND gate inputs to the bus
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pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", input_name])
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self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets)
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out_pos = self.pre_p_en_inst.get_pin("Z").center()
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in_pos = self.p_en_bar_inst.get_pin("A").lc()
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mid1 = vector(out_pos.x,in_pos.y)
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self.add_wire(("metal1","via1","metal2"),[out_pos,mid1,in_pos])
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in_map = zip(["A"], ["gated_clk_buf"])
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self.connect_vertical_bus(in_map, self.p_en_bar_inst, self.rail_offsets)
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self.connect_output(self.p_en_bar_inst, "Z", "p_en_bar")
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