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DRC and LVS fixes for pinv_dec

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mrg
2020-06-12 15:23:51 -07:00
parent 443b8fbe23
commit 33a32101c9
5 changed files with 60 additions and 27 deletions
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compiler/tests/04_pinv_dec_1x_test.py
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@@ -21,6 +21,11 @@ class pinv_dec_1x_test(openram_test):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Checking 1x size decoder inverter")
tx = factory.create(module_type="pinv_dec", size=1)
self.local_check(tx)