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Do not run same well spacing for backwards compatibility. Add pbitcell cheat.

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mrg
2021-11-22 11:33:27 -08:00
parent 48e35588f4
commit 32c7e90662
1 changed files with 3 additions and 3 deletions
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technology/scn4m_subm/tech/tech.py
+3 -3
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@@ -428,8 +428,8 @@ spice["sa_transconductance"] = (spice["mobility_n"])*spice["cox"]*(parameter["sa
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"
drc_name = "klayout"
lvs_name = "klayout"
pex_name = "klayout"
# drc_name = "klayout"
# lvs_name = "klayout"
# pex_name = "klayout"
blackbox_bitcell = False