Add initial support and unit tests for 2 port SRAM

2026-08-30 01:48:33 +02:00 · 2018-11-14 17:05:23 -08:00
parent 6ac5adaeca
commit 3221d3e744
5 changed files with 171 additions and 47 deletions
@@ -61,7 +61,8 @@ class bank(design.design):
        #self.add_lvs_correspondence_points() 

        # Remember the bank center for further placement
-        self.bank_center=self.offset_all_coordinates().scale(-1,-1)
+        self.bank_array_ll = self.offset_all_coordinates().scale(-1,-1)
+        self.bank_array_ur = self.bitcell_array_inst.ur()
        
        self.DRC_LVS()