mirror of https://github.com/VLSIDA/OpenRAM.git
Sized inverter for number of driven write drivers.
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@ -64,7 +64,9 @@ class write_mask_and_array(design.design):
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self.add_pin("gnd","GROUND")
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self.add_pin("gnd","GROUND")
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def add_modules(self):
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def add_modules(self):
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self.and2 = factory.create(module_type="pand2")
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# Size the AND gate for the number of write drivers it drives, which is equal to the write size.
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self.and2 = factory.create(module_type="pand2",
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size=self.write_size)
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self.add_mod(self.and2)
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self.add_mod(self.and2)
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