From 30a77f8527fa72da8e721ebbe67b5b193895d0ae Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 11:01:30 -0700 Subject: [PATCH] Convert scn3me_subm tech to lambda rules --- technology/scn3me_subm/tech/tech.py | 97 +++++++++++++++-------------- 1 file changed, 49 insertions(+), 48 deletions(-) diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index 463f4243..52c602cf 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -50,17 +50,18 @@ layer["blockage"] = 83 ################################################### ##DRC/LVS Rules Setup ################################################### +_lambda_ = 0.3 #technology parameter parameter={} -parameter["min_tx_size"] = 1.2 +parameter["min_tx_size"] = 4*_lambda_ parameter["beta"] = 2 drclvs_home=os.environ.get("DRCLVS_HOME") drc={} #grid size is 1/2 a lambda -drc["grid"]=0.15 +drc["grid"]=0.5*_lambda_ #DRC/LVS test set_up drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul" drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul" @@ -68,52 +69,52 @@ drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map" # minwidth_tx with contact (no dog bone transistors) -drc["minwidth_tx"] = 1.2 -drc["minlength_channel"] = 0.6 +drc["minwidth_tx"] = 4*_lambda_ +drc["minlength_channel"] = 2*_lambda_ # 1.3 Minimum spacing between wells of same type (if both are drawn) -drc["well_to_well"] = 1.8 +drc["well_to_well"] = 6*_lambda_ # 1.4 Minimum spacing between wells of different type (if both are drawn) drc["pwell_to_nwell"] = 0 # 1.1 Minimum width -drc["minwidth_well"] = 3.6 +drc["minwidth_well"] = 12*_lambda_ # 3.1 Minimum width -drc["minwidth_poly"] = 0.6 +drc["minwidth_poly"] = 2*_lambda_ # 3.2 Minimum spacing over active -drc["poly_to_poly"] = 0.9 +drc["poly_to_poly"] = 3*_lambda_ # 3.3 Minimum gate extension of active -drc["poly_extend_active"] = 0.6 +drc["poly_extend_active"] = 2*_lambda_ # 5.5.b Minimum spacing between poly contact and other poly (alternative rules) -drc["poly_to_polycontact"] = 1.2 +drc["poly_to_polycontact"] = 4*_lambda_ # ?? drc["active_enclosure_gate"] = 0.0 # 3.5 Minimum field poly to active -drc["poly_to_active"] = 0.3 +drc["poly_to_active"] = _lambda_ # 3.2.a Minimum spacing over field poly -drc["poly_to_field_poly"] = 0.9 +drc["poly_to_field_poly"] = 3*_lambda_ # Not a rule drc["minarea_poly"] = 0.0 # ?? -drc["active_to_body_active"] = 1.2 # Fix me +drc["active_to_body_active"] = 4*_lambda_ # Fix me # 2.1 Minimum width -drc["minwidth_active"] = 0.9 +drc["minwidth_active"] = 3*_lambda_ # 2.2 Minimum spacing -drc["active_to_active"] = 0.9 +drc["active_to_active"] = 3*_lambda_ # 2.3 Source/drain active to well edge -drc["well_enclosure_active"] = 1.8 +drc["well_enclosure_active"] = 6*_lambda_ # Reserved for asymmetric enclosures -drc["well_extend_active"] = 1.8 +drc["well_extend_active"] = 6*_lambda_ # Not a rule drc["minarea_active"] = 0.0 # 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width -drc["implant_to_channel"] = 0.9 +drc["implant_to_channel"] = 3*_lambda_ # 4.2 Minimum select overlap of active -drc["implant_enclosure_active"] = 0.6 +drc["implant_enclosure_active"] = 2*_lambda_ # 4.3 Minimum select overlap of contact -drc["implant_enclosure_contact"] = 0.3 +drc["implant_enclosure_contact"] = _lambda_ # Not a rule drc["implant_to_contact"] = 0 # Not a rule @@ -122,70 +123,70 @@ drc["implant_to_implant"] = 0 drc["minwidth_implant"] = 0 # 6.1 Exact contact size -drc["minwidth_contact"] = 0.6 +drc["minwidth_contact"] = 2*_lambda_ # 5.3 Minimum contact spacing -drc["contact_to_contact"] = 0.9 +drc["contact_to_contact"] = 3*_lambda_ # 6.2.b Minimum active overlap -drc["active_enclosure_contact"] = 0.3 +drc["active_enclosure_contact"] = _lambda_ # Reserved for asymmetric enclosure -drc["active_extend_contact"] = 0.3 +drc["active_extend_contact"] = _lambda_ # 5.2.b Minimum poly overlap -drc["poly_enclosure_contact"] = 0.3 +drc["poly_enclosure_contact"] = _lambda_ # Reserved for asymmetric enclosures -drc["poly_extend_contact"] = 0.3 +drc["poly_extend_contact"] = _lambda_ # Reserved for other technologies -drc["contact_to_gate"] = 0.6 +drc["contact_to_gate"] = 2*_lambda_ # 5.4 Minimum spacing to gate of transistor -drc["contact_to_poly"] = 0.6 +drc["contact_to_poly"] = 2*_lambda_ # 7.1 Minimum width -drc["minwidth_metal1"] = 0.9 +drc["minwidth_metal1"] = 3*_lambda_ # 7.2 Minimum spacing -drc["metal1_to_metal1"] = 0.9 +drc["metal1_to_metal1"] = 3*_lambda_ # 7.3 Minimum overlap of any contact -drc["metal1_enclosure_contact"] = 0.3 +drc["metal1_enclosure_contact"] = _lambda_ # Reserved for asymmetric enclosure -drc["metal1_extend_contact"] = 0.3 +drc["metal1_extend_contact"] = _lambda_ # 8.3 Minimum overlap by metal1 -drc["metal1_enclosure_via1"] = 0.3 +drc["metal1_enclosure_via1"] = _lambda_ # Reserve for asymmetric enclosures -drc["metal1_extend_via1"] = 0.3 +drc["metal1_extend_via1"] = _lambda_ # Not a rule drc["minarea_metal1"] = 0 # 8.1 Exact size -drc["minwidth_via1"] = 0.6 +drc["minwidth_via1"] = 2*_lambda_ # 8.2 Minimum via1 spacing -drc["via1_to_via1"] = 0.6 +drc["via1_to_via1"] = 2*_lambda_ # 9.1 Minimum width -drc["minwidth_metal2"] = 0.9 +drc["minwidth_metal2"] = 3*_lambda_ # 9.2 Minimum spacing -drc["metal2_to_metal2"] = 0.9 +drc["metal2_to_metal2"] = 3*_lambda_ # 9.3 Minimum overlap of via1 -drc["metal2_extend_via1"] = 0.3 +drc["metal2_extend_via1"] = _lambda_ # Reserved for asymmetric enclosures -drc["metal2_enclosure_via1"] = 0.3 +drc["metal2_enclosure_via1"] = _lambda_ # 14.3 Minimum overlap by metal2 -drc["metal2_extend_via2"] = 0.3 +drc["metal2_extend_via2"] = _lambda_ # Reserved for asymmetric enclosures -drc["metal2_enclosure_via2"] = 0.3 +drc["metal2_enclosure_via2"] = _lambda_ # Not a rule drc["minarea_metal2"] = 0 # 14.2 Exact size -drc["minwidth_via2"] = 0.6 +drc["minwidth_via2"] = 2*_lambda_ # 14.2 Minimum spacing -drc["via2_to_via2"] = 0.9 +drc["via2_to_via2"] = 3*_lambda_ # 15.1 Minimum width -drc["minwidth_metal3"] = 1.5 +drc["minwidth_metal3"] = 5*_lambda_ # 15.2 Minimum spacing to metal3 -drc["metal3_to_metal3"] = 0.9 +drc["metal3_to_metal3"] = 3*_lambda_ # 15.3 Minimum overlap of via 2 -drc["metal3_extend_via2"] = 0.6 +drc["metal3_extend_via2"] = 2*_lambda_ # Reserved for asymmetric enclosures -drc["metal3_enclosure_via2"] = 0.6 +drc["metal3_enclosure_via2"] = 2*_lambda_ # Not a rule drc["minarea_metal3"] = 0