mirror of https://github.com/VLSIDA/OpenRAM.git
Fix update to exclude bits with RBLs
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@ -501,7 +501,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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def graph_exclude_replica_col_bits(self):
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def graph_exclude_replica_col_bits(self):
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"""Exclude all replica/dummy cells in the replica columns except the replica bit."""
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"""Exclude all replica/dummy cells in the replica columns except the replica bit."""
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for port in range(self.left_rbl + self.right_rbl):
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for port in self.left_rbl + self.right_rbl:
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self.replica_columns[port].exclude_all_but_replica()
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self.replica_columns[port].exclude_all_but_replica()
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def get_cell_name(self, inst_name, row, col):
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def get_cell_name(self, inst_name, row, col):
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