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PEP8 cleanup

This commit is contained in:
mrg 2020-11-17 16:56:00 -08:00
parent 02c1fac3b8
commit 305b546ad5
1 changed files with 7 additions and 9 deletions
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2
compiler/base/verilog.py
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@ -84,7 +84,6 @@ class verilog:
self.vf.write("endmodule\n") self.vf.write("endmodule\n")
self.vf.close() self.vf.close()
def register_inputs(self, port): def register_inputs(self, port):
""" """
Register the control signal, address and data inputs. Register the control signal, address and data inputs.
@ -151,7 +150,6 @@ class verilog:
self.vf.write(" end\n\n") self.vf.write(" end\n\n")
def add_inputs_outputs(self, port): def add_inputs_outputs(self, port):
""" """
Add the module input and output declaration for a port. Add the module input and output declaration for a port.