diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py
index 9760d6a1..989d9d9c 100644
--- a/compiler/base/verilog.py
+++ b/compiler/base/verilog.py
@@ -84,7 +84,6 @@ class verilog:
         self.vf.write("endmodule\n")
         self.vf.close()
 
-
     def register_inputs(self, port):
         """
         Register the control signal, address and data inputs.
@@ -129,7 +128,7 @@ class verilog:
         if port in self.write_ports:
             self.vf.write("    din{0}_reg = din{0};\n".format(port))
         if port in self.read_ports:
-            self.vf.write("    dout{0} = {1}'bx;\n".format(port,self.word_size))
+            self.vf.write("    dout{0} = {1}'bx;\n".format(port, self.word_size))
         if port in self.readwrite_ports:
             self.vf.write("    if ( !csb{0}_reg && web{0}_reg ) \n".format(port))
             self.vf.write("      $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port))
@@ -151,7 +150,6 @@ class verilog:
 
         self.vf.write("  end\n\n")
 
-
     def add_inputs_outputs(self, port):
         """
         Add the module input and output declaration for a port.
@@ -191,14 +189,14 @@ class verilog:
 
         if self.write_size:
             remainder_bits = self.word_size % self.write_size
-            for mask in range(0,self.num_wmasks):
+            for mask in range(0, self.num_wmasks):
                 lower = mask * self.write_size
                 if (remainder_bits and mask == self.num_wmasks - 1):
                     upper = lower + remainder_bits - 1
                 else:
                     upper = lower + self.write_size - 1
-                self.vf.write("        if (wmask{0}_reg[{1}])\n".format(port,mask))
-                self.vf.write("                mem[addr{0}_reg][{1}:{2}] = din{0}_reg[{1}:{2}];\n".format(port,upper,lower))
+                self.vf.write("        if (wmask{0}_reg[{1}])\n".format(port, mask))
+                self.vf.write("                mem[addr{0}_reg][{1}:{2}] = din{0}_reg[{1}:{2}];\n".format(port, upper, lower))
             self.vf.write("    end\n")
         else:
             self.vf.write("        mem[addr{0}_reg] = din{0}_reg;\n".format(port))
@@ -232,8 +230,8 @@ class verilog:
         else:
             wport_control = "!csb{0}".format(wport)
 
-        self.vf.write("    if ({1} && {3} && (addr{0} == addr{2}))\n".format(wport,wport_control,rport,rport_control))
-        self.vf.write("         $display($time,\" WARNING: Writing and reading addr{0}=%b and addr{1}=%b simultaneously!\",addr{0},addr{1});\n".format(wport,rport))
+        self.vf.write("    if ({1} && {3} && (addr{0} == addr{2}))\n".format(wport, wport_control, rport, rport_control))
+        self.vf.write("         $display($time,\" WARNING: Writing and reading addr{0}=%b and addr{1}=%b simultaneously!\",addr{0},addr{1});\n".format(wport, rport))
 
     def add_write_read_checks(self, rport):
         """
@@ -244,4 +242,4 @@ class verilog:
             if wport == rport:
                 continue
             else:
-                self.add_address_check(wport,rport)
+                self.add_address_check(wport, rport)