mirror of https://github.com/VLSIDA/OpenRAM.git
Fix ptx so nmos and pmos have same active offset and gates align
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@ -75,8 +75,10 @@ class pgate(design.design):
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pmos_gate_pin = pmos_inst.get_pin("G")
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pmos_gate_pin = pmos_inst.get_pin("G")
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# Check if the gates are aligned and give an error if they aren't!
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# Check if the gates are aligned and give an error if they aren't!
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if nmos_gate_pin.ll().x != pmos_gate_pin.ll().x:
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self.gds_write("unaliged_gates.gds")
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debug.check(nmos_gate_pin.ll().x == pmos_gate_pin.ll().x,
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debug.check(nmos_gate_pin.ll().x == pmos_gate_pin.ll().x,
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"Connecting unaligned gates not supported.")
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"Connecting unaligned gates not supported. See unaligned_gates.gds.")
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# Pick point on the left of NMOS and connect down to PMOS
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# Pick point on the left of NMOS and connect down to PMOS
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nmos_gate_pos = nmos_gate_pin.ll() + vector(0.5 * self.poly_width, 0)
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nmos_gate_pos = nmos_gate_pin.ll() + vector(0.5 * self.poly_width, 0)
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@ -156,13 +156,17 @@ class ptx(design.design):
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self.poly_height = self.tx_width + 2 * self.poly_extend_active
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self.poly_height = self.tx_width + 2 * self.poly_extend_active
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# The active offset is due to the well extension
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# The active offset is due to the well extension
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# but we need to do the active offset for the other tx type too
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if "pwell" in layer:
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# so that they align in pgates.
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pwell_enclose_active = drc("pwell_enclose_active")
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well_enclose_active = 0
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else:
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if self.well_type=="p" and "pwell" in layer:
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pwell_enclose_active = 0
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well_enclose_active = max(drc("pwell_enclose_active"), well_enclose_active)
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if "nwell" in layer:
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if self.well_type=="n" and "nwell" in layer:
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nwell_enclose_active = drc("nwell_enclose_active")
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well_enclose_active = max(drc("nwell_enclose_active"), well_enclose_active)
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else:
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nwell_enclose_active = 0
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# Use the max of either so that the poly gates will align properly
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well_enclose_active = max(pwell_enclose_active,
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nwell_enclose_active)
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self.active_offset = vector([well_enclose_active] * 2)
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self.active_offset = vector([well_enclose_active] * 2)
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# Well enclosure of active, ensure minwidth as well
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# Well enclosure of active, ensure minwidth as well
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