diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py
index cac2ee9d..ab30a0d0 100644
--- a/compiler/pgates/pgate.py
+++ b/compiler/pgates/pgate.py
@@ -75,8 +75,10 @@ class pgate(design.design):
         pmos_gate_pin = pmos_inst.get_pin("G")
 
         # Check if the gates are aligned and give an error if they aren't!
+        if nmos_gate_pin.ll().x != pmos_gate_pin.ll().x:
+            self.gds_write("unaliged_gates.gds")
         debug.check(nmos_gate_pin.ll().x == pmos_gate_pin.ll().x,
-                    "Connecting unaligned gates not supported.")
+                    "Connecting unaligned gates not supported. See unaligned_gates.gds.")
         
         # Pick point on the left of NMOS and connect down to PMOS
         nmos_gate_pos = nmos_gate_pin.ll() + vector(0.5 * self.poly_width, 0)
diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py
index 3af456e0..f331dc28 100644
--- a/compiler/pgates/ptx.py
+++ b/compiler/pgates/ptx.py
@@ -156,13 +156,17 @@ class ptx(design.design):
         self.poly_height = self.tx_width + 2 * self.poly_extend_active
         
         # The active offset is due to the well extension
-        # but we need to do the active offset for the other tx type too
-        # so that they align in pgates.
-        well_enclose_active = 0
-        if self.well_type=="p" and "pwell" in layer:
-            well_enclose_active = max(drc("pwell_enclose_active"), well_enclose_active)
-        if self.well_type=="n" and "nwell" in layer:
-            well_enclose_active = max(drc("nwell_enclose_active"), well_enclose_active)
+        if "pwell" in layer:
+            pwell_enclose_active = drc("pwell_enclose_active")
+        else:
+            pwell_enclose_active = 0
+        if "nwell" in layer:
+            nwell_enclose_active = drc("nwell_enclose_active")
+        else:
+            nwell_enclose_active = 0
+        # Use the max of either so that the poly gates will align properly
+        well_enclose_active = max(pwell_enclose_active,
+                                  nwell_enclose_active)
         self.active_offset = vector([well_enclose_active] * 2)
 
         # Well enclosure of active, ensure minwidth as well