mirror of https://github.com/VLSIDA/OpenRAM.git
rotate input to rail contacts for drc
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parent
247a388ab5
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2e72da0e53
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@ -215,12 +215,16 @@ class hierarchical_predecode(design.design):
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in_pos = vector(self.input_rails[in_pin].cx(), y_offset)
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in_pos = vector(self.input_rails[in_pin].cx(), y_offset)
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a_pos = vector(self.decode_rails[a_pin].cx(), y_offset)
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a_pos = vector(self.decode_rails[a_pin].cx(), y_offset)
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self.add_path(self.input_layer, [in_pos, a_pos])
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self.add_path(self.input_layer, [in_pos, a_pos])
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self.add_via_stack_center(from_layer=self.input_layer,
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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to_layer=self.bus_layer,
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offset=[self.input_rails[in_pin].cx(), y_offset])
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offset=[self.input_rails[in_pin].cx(), y_offset],
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directions= ("H", "H"))
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self.add_via_stack_center(from_layer=self.input_layer,
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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to_layer=self.bus_layer,
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offset=[self.decode_rails[a_pin].cx(), y_offset])
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offset=[self.decode_rails[a_pin].cx(), y_offset],
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directions=("H", "H"))
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def route_output_ands(self):
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def route_output_ands(self):
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"""
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"""
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