mirror of https://github.com/VLSIDA/OpenRAM.git
First pass of multiple bitcells per decoder row
This commit is contained in:
mrg
parent
7888e54fc4
commit
2e67d44cd7
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@ -32,11 +32,11 @@ class hierarchical_decoder(design.design):
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self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple
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self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple
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except AttributeError:
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except AttributeError:
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self.cell_multiple = 1
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self.cell_multiple = 1
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# For debugging
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# self.cell_multiple = 2
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self.cell_height = self.cell_multiple * b.height
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self.cell_height = self.cell_multiple * b.height
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self.num_outputs = num_outputs
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self.num_outputs = num_outputs
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# We may have more than one bitcell per decoder row
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self.rows = math.ceil(num_outputs / self.cell_multiple)
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self.num_inputs = math.ceil(math.log(self.num_outputs, 2))
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self.num_inputs = math.ceil(math.log(self.num_outputs, 2))
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(self.no_of_pre2x4, self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs)
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(self.no_of_pre2x4, self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs)
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@ -52,6 +52,10 @@ class hierarchical_decoder(design.design):
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"""
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"""
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b = factory.create(module_type="bitcell")
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b = factory.create(module_type="bitcell")
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# Old behavior
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if OPTS.netlist_only:
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return (b.height, 1)
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# Search for the smallest multiple that works
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# Search for the smallest multiple that works
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cell_multiple = 1
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cell_multiple = 1
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while cell_multiple < 5:
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while cell_multiple < 5:
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@ -86,8 +90,8 @@ class hierarchical_decoder(design.design):
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self.setup_layout_constants()
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self.setup_layout_constants()
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self.place_pre_decoder()
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self.place_pre_decoder()
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self.place_row_decoder()
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self.place_row_decoder()
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self.route_input_rails()
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self.route_inputs()
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self.route_predecode_rails()
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self.route_decoder_bus()
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self.route_vdd_gnd()
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self.route_vdd_gnd()
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self.offset_all_coordinates()
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self.offset_all_coordinates()
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self.add_boundary()
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self.add_boundary()
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@ -141,7 +145,7 @@ class hierarchical_decoder(design.design):
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def setup_netlist_constants(self):
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def setup_netlist_constants(self):
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self.predec_groups = [] # This array is a 2D array.
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self.predec_groups = [] # This array is a 2D array.
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# Distributing vertical rails to different groups. One group belongs to one pre-decoder.
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# Distributing vertical bus to different groups. One group belongs to one pre-decoder.
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# For example, for two 2:4 pre-decoder and one 3:8 pre-decoder, we will
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# For example, for two 2:4 pre-decoder and one 3:8 pre-decoder, we will
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# have total 16 output lines out of these 3 pre-decoders and they will
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# have total 16 output lines out of these 3 pre-decoders and they will
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# be distributed as [ [0,1,2,3] ,[4,5,6,7], [8,9,10,11,12,13,14,15] ]
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# be distributed as [ [0,1,2,3] ,[4,5,6,7], [8,9,10,11,12,13,14,15] ]
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@ -180,35 +184,41 @@ class hierarchical_decoder(design.design):
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self.predecoder_height = self.pre2_4.height * self.no_of_pre2x4 + self.pre3_8.height * self.no_of_pre3x8
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self.predecoder_height = self.pre2_4.height * self.no_of_pre2x4 + self.pre3_8.height * self.no_of_pre3x8
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# We may have more than one bitcell per decoder row
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self.num_rows = math.ceil(self.num_outputs / self.cell_multiple)
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# We will place this many final decoders per row
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self.decoders_per_row = math.ceil(self.num_outputs / self.num_rows)
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# Calculates height and width of row-decoder
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# Calculates height and width of row-decoder
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if (self.num_inputs == 4 or self.num_inputs == 5):
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if (self.num_inputs == 4 or self.num_inputs == 5):
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nand_width = self.and2.width
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nand_width = self.and2.width
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else:
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else:
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nand_width = self.and3.width
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nand_width = self.and3.width
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self.internal_routing_width = self.m2_pitch * self.total_number_of_predecoder_outputs
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self.internal_routing_width = self.m2_pitch * (self.total_number_of_predecoder_outputs + 1)
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self.row_decoder_height = self.inv.height * self.rows
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self.row_decoder_height = self.inv.height * self.num_rows
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self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch
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self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch
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# Calculates height and width of hierarchical decoder
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# Calculates height and width of hierarchical decoder
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self.height = self.row_decoder_height
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self.height = max(self.predecoder_height, self.row_decoder_height)
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self.width = self.input_routing_width + self.predecoder_width \
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self.width = self.input_routing_width + self.predecoder_width \
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+ self.internal_routing_width + nand_width + self.inv.width
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+ self.internal_routing_width \
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+ self.decoders_per_row * nand_width + self.inv.width
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def route_input_rails(self):
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def route_inputs(self):
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""" Create input rails for the predecoders """
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""" Create input bus for the predecoders """
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# inputs should be as high as the decoders
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# inputs should be as high as the decoders
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input_height = self.no_of_pre2x4 * self.pre2_4.height + self.no_of_pre3x8 * self.pre3_8.height
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input_height = self.no_of_pre2x4 * self.pre2_4.height + self.no_of_pre3x8 * self.pre3_8.height
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# Find the left-most predecoder
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# Find the left-most predecoder
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min_x = 0
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min_x = 0
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if self.no_of_pre2x4 > 0:
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if self.no_of_pre2x4 > 0:
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min_x = min(min_x, -self.pre2_4.width)
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min_x = min(min_x, self.pre2x4_inst[0].lx())
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if self.no_of_pre3x8 > 0:
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if self.no_of_pre3x8 > 0:
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min_x = min(min_x, -self.pre3_8.width)
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min_x = min(min_x, self.pre3x8_inst[0].lx())
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input_offset=vector(min_x - self.input_routing_width, 0)
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input_offset=vector(min_x - self.input_routing_width, 0)
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input_bus_names = ["addr_{0}".format(i) for i in range(self.num_inputs)]
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input_bus_names = ["addr_{0}".format(i) for i in range(self.num_inputs)]
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self.input_rails = self.create_vertical_pin_bus(layer="m2",
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self.input_bus = self.create_vertical_pin_bus(layer="m2",
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pitch=self.m2_pitch,
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pitch=self.m2_pitch,
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offset=input_offset,
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offset=input_offset,
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names=input_bus_names,
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names=input_bus_names,
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@ -222,7 +232,7 @@ class hierarchical_decoder(design.design):
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for i in range(2):
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for i in range(2):
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index = pre_num * 2 + i
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index = pre_num * 2 + i
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input_pos = self.input_rails["addr_{}".format(index)]
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input_pos = self.input_bus["addr_{}".format(index)]
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in_name = "in_{}".format(i)
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in_name = "in_{}".format(i)
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decoder_pin = self.pre2x4_inst[pre_num].get_pin(in_name)
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decoder_pin = self.pre2x4_inst[pre_num].get_pin(in_name)
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@ -232,13 +242,13 @@ class hierarchical_decoder(design.design):
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decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height)
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decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height)
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input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1)
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input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1)
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self.route_input_rail(decoder_offset, input_offset)
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self.route_input_bus(decoder_offset, input_offset)
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for pre_num in range(self.no_of_pre3x8):
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for pre_num in range(self.no_of_pre3x8):
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for i in range(3):
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for i in range(3):
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index = pre_num * 3 + i + self.no_of_pre2x4 * 2
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index = pre_num * 3 + i + self.no_of_pre2x4 * 2
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input_pos = self.input_rails["addr_{}".format(index)]
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input_pos = self.input_bus["addr_{}".format(index)]
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in_name = "in_{}".format(i)
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in_name = "in_{}".format(i)
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decoder_pin = self.pre3x8_inst[pre_num].get_pin(in_name)
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decoder_pin = self.pre3x8_inst[pre_num].get_pin(in_name)
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@ -248,9 +258,9 @@ class hierarchical_decoder(design.design):
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decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height)
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decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height)
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input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1)
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input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1)
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self.route_input_rail(decoder_offset, input_offset)
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self.route_input_bus(decoder_offset, input_offset)
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def route_input_rail(self, input_offset, output_offset):
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def route_input_bus(self, input_offset, output_offset):
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""" Route a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """
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""" Route a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """
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self.add_via_center(layers=self.m2_stack,
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self.add_via_center(layers=self.m2_stack,
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@ -334,18 +344,17 @@ class hierarchical_decoder(design.design):
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else:
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else:
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base= vector(-self.pre2_4.width, num * self.pre2_4.height)
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base= vector(-self.pre2_4.width, num * self.pre2_4.height)
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self.pre2x4_inst[num].place(base)
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self.pre2x4_inst[num].place(base - vector(2 * self.m2_pitch, 0))
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def place_pre3x8(self, num):
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def place_pre3x8(self, num):
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""" Place 3x8 predecoder to the left of the origin and above any 2x4 decoders """
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""" Place 3x8 predecoder to the left of the origin and above any 2x4 decoders """
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if (self.num_inputs == 3):
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if (self.num_inputs == 3):
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offset = vector(-self.pre_3_8.width, 0)
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offset = vector(-self.pre_3_8.width, 0)
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mirror = "R0"
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else:
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else:
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height = self.no_of_pre2x4 * self.pre2_4.height + num * self.pre3_8.height
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height = self.no_of_pre2x4 * self.pre2_4.height + num * self.pre3_8.height
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offset = vector(-self.pre3_8.width, height)
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offset = vector(-self.pre3_8.width, height)
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self.pre3x8_inst[num].place(offset)
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self.pre3x8_inst[num].place(offset - vector(2 * self.m2_pitch, 0))
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def create_row_decoder(self):
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def create_row_decoder(self):
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""" Create the row-decoder by placing AND2/AND3 and Inverters
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""" Create the row-decoder by placing AND2/AND3 and Inverters
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@ -362,14 +371,14 @@ class hierarchical_decoder(design.design):
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if (self.num_inputs == 4 or self.num_inputs == 5):
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if (self.num_inputs == 4 or self.num_inputs == 5):
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for i in range(len(self.predec_groups[0])):
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for i in range(len(self.predec_groups[0])):
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for j in range(len(self.predec_groups[1])):
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for j in range(len(self.predec_groups[1])):
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row = len(self.predec_groups[0]) * j + i
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output = len(self.predec_groups[0]) * j + i
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if (row < self.num_outputs):
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if (output < self.num_outputs):
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name = self.AND_FORMAT.format(row)
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name = self.AND_FORMAT.format(output)
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self.and_inst.append(self.add_inst(name=name,
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self.and_inst.append(self.add_inst(name=name,
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mod=self.and2))
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mod=self.and2))
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pins =["out_{0}".format(i),
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pins =["out_{0}".format(i),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"decode_{0}".format(row),
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"decode_{0}".format(output),
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"vdd", "gnd"]
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"vdd", "gnd"]
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self.connect_inst(pins)
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self.connect_inst(pins)
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@ -378,18 +387,18 @@ class hierarchical_decoder(design.design):
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for i in range(len(self.predec_groups[0])):
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for i in range(len(self.predec_groups[0])):
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for j in range(len(self.predec_groups[1])):
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for j in range(len(self.predec_groups[1])):
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for k in range(len(self.predec_groups[2])):
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for k in range(len(self.predec_groups[2])):
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row = (len(self.predec_groups[0]) * len(self.predec_groups[1])) * k \
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output = (len(self.predec_groups[0]) * len(self.predec_groups[1])) * k \
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+ len(self.predec_groups[0]) * j + i
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+ len(self.predec_groups[0]) * j + i
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if (row < self.num_outputs):
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if (output < self.num_outputs):
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name = self.AND_FORMAT.format(row)
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name = self.AND_FORMAT.format(output)
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self.and_inst.append(self.add_inst(name=name,
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self.and_inst.append(self.add_inst(name=name,
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mod=self.and3))
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mod=self.and3))
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pins = ["out_{0}".format(i),
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pins = ["out_{0}".format(i),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"out_{0}".format(k + len(self.predec_groups[0]) + len(self.predec_groups[1])),
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"out_{0}".format(k + len(self.predec_groups[0]) + len(self.predec_groups[1])),
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"decode_{0}".format(row),
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"decode_{0}".format(output),
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"vdd", "gnd"]
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"vdd", "gnd"]
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self.connect_inst(pins)
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self.connect_inst(pins)
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self.route_decoder()
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self.route_decoder()
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def place_decoder_and_array(self):
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def place_decoder_and_array(self):
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""" Add a column of AND gates for final decode """
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"""
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Add a column of AND gates for final decode.
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This may have more than one decoder per row to match the bitcell height.
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"""
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# Row Decoder AND GATE array for address inputs <5.
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# Row Decoder AND GATE array for address inputs <5.
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if (self.num_inputs == 4 or self.num_inputs == 5):
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if (self.num_inputs == 4 or self.num_inputs == 5):
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self.place_and_array(and_mod=self.and3)
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self.place_and_array(and_mod=self.and3)
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def place_and_array(self, and_mod):
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def place_and_array(self, and_mod):
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""" Add a column of AND gates for the decoder above the predecoders."""
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"""
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Add a column of AND gates for the decoder above the predecoders.
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"""
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for row in range(self.num_outputs):
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for inst_index in range(self.num_outputs):
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row = math.floor(inst_index / self.decoders_per_row)
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dec = inst_index % self.decoders_per_row
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if ((row % 2) == 0):
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if ((row % 2) == 0):
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y_off = and_mod.height * row
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y_off = and_mod.height * row
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mirror = "R0"
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mirror = "R0"
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y_off = and_mod.height * (row + 1)
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y_off = and_mod.height * (row + 1)
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mirror = "MX"
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mirror = "MX"
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self.and_inst[row].place(offset=[self.internal_routing_width, y_off],
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x_off = self.internal_routing_width + dec * and_mod.width
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self.and_inst[inst_index].place(offset=vector(x_off, y_off),
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mirror=mirror)
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mirror=mirror)
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def route_decoder(self):
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def route_decoder(self):
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""" Add the pins. """
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""" Add the pins. """
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for row in range(self.num_outputs):
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for output in range(self.num_outputs):
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z_pin = self.and_inst[row].get_pin("Z")
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z_pin = self.and_inst[output].get_pin("Z")
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self.add_layout_pin(text="decode_{0}".format(row),
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self.add_layout_pin(text="decode_{0}".format(output),
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layer="m1",
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layer="m1",
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offset=z_pin.ll(),
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offset=z_pin.ll(),
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width=z_pin.width(),
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width=z_pin.width(),
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height=z_pin.height())
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height=z_pin.height())
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def route_predecode_rails(self):
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def route_decoder_bus(self):
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""" Creates vertical metal 2 rails to connect predecoder and decoder stages."""
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"""
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Creates vertical metal 2 bus to connect predecoder and decoder stages.
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"""
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# This is not needed for inputs <4 since they have no pre/decode stages.
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# This is not needed for inputs <4 since they have no pre/decode stages.
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if (self.num_inputs >= 4):
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if (self.num_inputs >= 4):
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input_offset = vector(0.5 * self.m2_width, 0)
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# This leaves an offset for the predecoder output jogs
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input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)]
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input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)]
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self.predecode_rails = self.create_vertical_pin_bus(layer="m2",
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self.predecode_bus = self.create_vertical_pin_bus(layer="m2",
|
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pitch=self.m2_pitch,
|
pitch=self.m2_pitch,
|
||||||
offset=input_offset,
|
offset=vector(0, 0),
|
||||||
names=input_bus_names,
|
names=input_bus_names,
|
||||||
length=self.height)
|
length=self.height)
|
||||||
|
|
||||||
self.route_rails_to_predecodes()
|
self.route_bus_to_predecodes()
|
||||||
self.route_rails_to_decoder()
|
self.route_bus_to_decoder()
|
||||||
|
|
||||||
def route_rails_to_predecodes(self):
|
|
||||||
""" Iterates through all of the predecodes and connects to the rails including the offsets """
|
|
||||||
|
|
||||||
|
def route_bus_to_predecodes(self):
|
||||||
|
"""
|
||||||
|
Iterates through all of the predecodes
|
||||||
|
and connects to the rails including the offsets
|
||||||
|
"""
|
||||||
# FIXME: convert to connect_bus
|
# FIXME: convert to connect_bus
|
||||||
for pre_num in range(self.no_of_pre2x4):
|
for pre_num in range(self.no_of_pre2x4):
|
||||||
for i in range(4):
|
for i in range(4):
|
||||||
predecode_name = "predecode_{}".format(pre_num * 4 + i)
|
predecode_name = "predecode_{}".format(pre_num * 4 + i)
|
||||||
out_name = "out_{}".format(i)
|
out_name = "out_{}".format(i)
|
||||||
pin = self.pre2x4_inst[pre_num].get_pin(out_name)
|
pin = self.pre2x4_inst[pre_num].get_pin(out_name)
|
||||||
self.route_predecode_rail_m3(predecode_name, pin)
|
x_offset = self.pre2x4_inst[pre_num].rx() + self.m2_pitch
|
||||||
|
self.route_predecode_bus_inputs(predecode_name, pin, x_offset)
|
||||||
|
|
||||||
# FIXME: convert to connect_bus
|
# FIXME: convert to connect_bus
|
||||||
for pre_num in range(self.no_of_pre3x8):
|
for pre_num in range(self.no_of_pre3x8):
|
||||||
|
|
@ -472,44 +494,68 @@ class hierarchical_decoder(design.design):
|
||||||
predecode_name = "predecode_{}".format(pre_num * 8 + i + self.no_of_pre2x4 * 4)
|
predecode_name = "predecode_{}".format(pre_num * 8 + i + self.no_of_pre2x4 * 4)
|
||||||
out_name = "out_{}".format(i)
|
out_name = "out_{}".format(i)
|
||||||
pin = self.pre3x8_inst[pre_num].get_pin(out_name)
|
pin = self.pre3x8_inst[pre_num].get_pin(out_name)
|
||||||
self.route_predecode_rail_m3(predecode_name, pin)
|
x_offset = self.pre3x8_inst[pre_num].rx() + self.m2_pitch
|
||||||
|
self.route_predecode_bus_inputs(predecode_name, pin, x_offset)
|
||||||
|
|
||||||
def route_rails_to_decoder(self):
|
def route_bus_to_decoder(self):
|
||||||
""" Use the self.predec_groups to determine the connections to the decoder AND gates.
|
|
||||||
Inputs of AND2/AND3 gates come from different groups.
|
|
||||||
For example for these groups [ [0,1,2,3] ,[4,5,6,7],
|
|
||||||
[8,9,10,11,12,13,14,15] ] the first AND3 inputs are connected to
|
|
||||||
[0,4,8] and second AND3 is connected to [0,4,9] ........... and the
|
|
||||||
128th AND3 is connected to [3,7,15]
|
|
||||||
"""
|
"""
|
||||||
row_index = 0
|
Use the self.predec_groups to determine the connections to the decoder AND gates.
|
||||||
|
Inputs of AND2/AND3 gates come from different groups.
|
||||||
|
For example for these groups
|
||||||
|
[ [0,1,2,3] ,[4,5,6,7], [8,9,10,11,12,13,14,15] ]
|
||||||
|
the first AND3 inputs are connected to [0,4,8],
|
||||||
|
second AND3 is connected to [0,4,9],
|
||||||
|
...
|
||||||
|
and the 128th AND3 is connected to [3,7,15]
|
||||||
|
"""
|
||||||
|
output_index = 0
|
||||||
|
|
||||||
if (self.num_inputs == 4 or self.num_inputs == 5):
|
if (self.num_inputs == 4 or self.num_inputs == 5):
|
||||||
for index_B in self.predec_groups[1]:
|
for index_B in self.predec_groups[1]:
|
||||||
for index_A in self.predec_groups[0]:
|
for index_A in self.predec_groups[0]:
|
||||||
# FIXME: convert to connect_bus?
|
# FIXME: convert to connect_bus?
|
||||||
if (row_index < self.num_outputs):
|
if (output_index < self.num_outputs):
|
||||||
|
row_index = math.floor(output_index / self.decoders_per_row)
|
||||||
|
row_remainder = (output_index % self.decoders_per_row)
|
||||||
|
row_offset = row_index * self.and_inst[0].height + (2 * row_remainder + 4) * self.m1_pitch
|
||||||
predecode_name = "predecode_{}".format(index_A)
|
predecode_name = "predecode_{}".format(index_A)
|
||||||
self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("A"))
|
self.route_predecode_bus_outputs(predecode_name,
|
||||||
|
self.and_inst[output_index].get_pin("A"),
|
||||||
|
row_offset)
|
||||||
predecode_name = "predecode_{}".format(index_B)
|
predecode_name = "predecode_{}".format(index_B)
|
||||||
self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("B"))
|
self.route_predecode_bus_outputs(predecode_name,
|
||||||
row_index = row_index + 1
|
self.and_inst[output_index].get_pin("B"),
|
||||||
|
row_offset + self.m1_pitch)
|
||||||
|
output_index = output_index + 1
|
||||||
|
|
||||||
elif (self.num_inputs > 5):
|
elif (self.num_inputs > 5):
|
||||||
for index_C in self.predec_groups[2]:
|
for index_C in self.predec_groups[2]:
|
||||||
for index_B in self.predec_groups[1]:
|
for index_B in self.predec_groups[1]:
|
||||||
for index_A in self.predec_groups[0]:
|
for index_A in self.predec_groups[0]:
|
||||||
# FIXME: convert to connect_bus?
|
# FIXME: convert to connect_bus?
|
||||||
if (row_index < self.num_outputs):
|
if (output_index < self.num_outputs):
|
||||||
|
row_index = math.floor(output_index / self.decoders_per_row)
|
||||||
|
row_remainder = (output_index % self.decoders_per_row)
|
||||||
|
row_offset = row_index * self.and_inst[0].height + (3 * row_remainder + 4) * self.m1_pitch
|
||||||
predecode_name = "predecode_{}".format(index_A)
|
predecode_name = "predecode_{}".format(index_A)
|
||||||
self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("A"))
|
self.route_predecode_bus_outputs(predecode_name,
|
||||||
|
self.and_inst[output_index].get_pin("A"),
|
||||||
|
row_offset)
|
||||||
predecode_name = "predecode_{}".format(index_B)
|
predecode_name = "predecode_{}".format(index_B)
|
||||||
self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("B"))
|
self.route_predecode_bus_outputs(predecode_name,
|
||||||
|
self.and_inst[output_index].get_pin("B"),
|
||||||
|
row_offset + self.m1_pitch)
|
||||||
predecode_name = "predecode_{}".format(index_C)
|
predecode_name = "predecode_{}".format(index_C)
|
||||||
self.route_predecode_rail(predecode_name, self.and_inst[row_index].get_pin("C"))
|
self.route_predecode_bus_outputs(predecode_name,
|
||||||
row_index = row_index + 1
|
self.and_inst[output_index].get_pin("C"),
|
||||||
|
row_offset + 2 * self.m1_pitch)
|
||||||
|
output_index = output_index + 1
|
||||||
|
|
||||||
def route_vdd_gnd(self):
|
def route_vdd_gnd(self):
|
||||||
""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
|
"""
|
||||||
|
Add a pin for each row of vdd/gnd which are
|
||||||
|
must-connects next level up.
|
||||||
|
"""
|
||||||
|
|
||||||
# The vias will be placed in the center and right of the cells, respectively.
|
# The vias will be placed in the center and right of the cells, respectively.
|
||||||
xoffset = self.and_inst[0].rx()
|
xoffset = self.and_inst[0].rx()
|
||||||
|
|
@ -526,23 +572,42 @@ class hierarchical_decoder(design.design):
|
||||||
self.copy_layout_pin(pre, "vdd")
|
self.copy_layout_pin(pre, "vdd")
|
||||||
self.copy_layout_pin(pre, "gnd")
|
self.copy_layout_pin(pre, "gnd")
|
||||||
|
|
||||||
def route_predecode_rail(self, rail_name, pin):
|
def route_predecode_bus_outputs(self, rail_name, pin, y_offset):
|
||||||
""" Connect the routing rail to the given metal1 pin """
|
"""
|
||||||
rail_pos = vector(self.predecode_rails[rail_name].x, pin.lc().y)
|
Connect the routing rail to the given metal1 pin
|
||||||
self.add_path("m1", [rail_pos, pin.lc()])
|
using a routing track at the given y_offset
|
||||||
|
|
||||||
|
"""
|
||||||
|
pin_pos = pin.center()
|
||||||
|
# If we have a single decoder per row, we can route on M1
|
||||||
|
if self.decoders_per_row == 1:
|
||||||
|
rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y)
|
||||||
|
self.add_path("m1", [rail_pos, pin_pos])
|
||||||
self.add_via_center(layers=self.m1_stack,
|
self.add_via_center(layers=self.m1_stack,
|
||||||
offset=rail_pos)
|
offset=rail_pos)
|
||||||
|
# If not, we must route over the decoder cells on M3
|
||||||
|
else:
|
||||||
|
rail_pos = vector(self.predecode_bus[rail_name].x, y_offset)
|
||||||
|
mid_pos = vector(pin_pos.x, rail_pos.y)
|
||||||
|
self.add_wire(self.m2_stack[::-1], [rail_pos, mid_pos, pin_pos])
|
||||||
|
self.add_via_center(layers=self.m2_stack,
|
||||||
|
offset=rail_pos)
|
||||||
|
self.add_via_center(layers=self.m1_stack,
|
||||||
|
offset=pin_pos)
|
||||||
|
|
||||||
def route_predecode_rail_m3(self, rail_name, pin):
|
def route_predecode_bus_inputs(self, rail_name, pin, x_offset):
|
||||||
""" Connect the routing rail to the given metal1 pin """
|
"""
|
||||||
|
Connect the routing rail to the given metal1 pin using a jog
|
||||||
|
to the right of the cell at the given x_offset.
|
||||||
|
"""
|
||||||
# This routes the pin up to the rail, basically, to avoid conflicts.
|
# This routes the pin up to the rail, basically, to avoid conflicts.
|
||||||
# It would be fixed with a channel router.
|
# It would be fixed with a channel router.
|
||||||
mid_point = vector(pin.cx(), pin.cy() + self.inv.height / 2)
|
pin_pos = pin.center()
|
||||||
rail_pos = vector(self.predecode_rails[rail_name].x, mid_point.y)
|
mid_point1 = vector(x_offset, pin_pos.y)
|
||||||
|
mid_point2 = vector(x_offset, pin_pos.y + self.inv.height / 2)
|
||||||
|
rail_pos = vector(self.predecode_bus[rail_name].x, mid_point2.y)
|
||||||
|
self.add_wire(self.m1_stack, [pin_pos, mid_point1, mid_point2, rail_pos])
|
||||||
self.add_via_center(layers=self.m1_stack,
|
self.add_via_center(layers=self.m1_stack,
|
||||||
offset=pin.center())
|
|
||||||
self.add_wire(("m3", "via2", "m2"), [rail_pos, mid_point, pin.uc()])
|
|
||||||
self.add_via_center(layers=self.m2_stack,
|
|
||||||
offset=rail_pos)
|
offset=rail_pos)
|
||||||
|
|
||||||
def input_load(self):
|
def input_load(self):
|
||||||
|
|
|
||||||
|
|
@ -221,7 +221,7 @@ class pnand3(pgate.pgate):
|
||||||
self.nmos3_inst,
|
self.nmos3_inst,
|
||||||
self.inputC_yoffset,
|
self.inputC_yoffset,
|
||||||
"C",
|
"C",
|
||||||
position="center")
|
position="left")
|
||||||
|
|
||||||
# FIXME: constant hack
|
# FIXME: constant hack
|
||||||
if OPTS.tech_name == "s8":
|
if OPTS.tech_name == "s8":
|
||||||
|
|
@ -232,7 +232,7 @@ class pnand3(pgate.pgate):
|
||||||
self.nmos1_inst,
|
self.nmos1_inst,
|
||||||
self.inputA_yoffset,
|
self.inputA_yoffset,
|
||||||
"A",
|
"A",
|
||||||
position="center")
|
position="left")
|
||||||
|
|
||||||
def route_output(self):
|
def route_output(self):
|
||||||
""" Route the Z output """
|
""" Route the Z output """
|
||||||
|
|
@ -255,10 +255,10 @@ class pnand3(pgate.pgate):
|
||||||
directions=("V", "V"))
|
directions=("V", "V"))
|
||||||
|
|
||||||
# PMOS3 and NMOS3 are drain aligned
|
# PMOS3 and NMOS3 are drain aligned
|
||||||
self.add_path("m2", [pmos3_pin.center(), nmos3_pin.center()])
|
self.add_path("m1", [pmos3_pin.center(), nmos3_pin.center()])
|
||||||
# Route in the A input track (top track)
|
# Route in the A input track (top track)
|
||||||
mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset)
|
mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset)
|
||||||
self.add_path("m2", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()])
|
self.add_path("m1", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()])
|
||||||
|
|
||||||
# This extends the output to the edge of the cell
|
# This extends the output to the edge of the cell
|
||||||
self.add_via_center(layers=self.m1_stack,
|
self.add_via_center(layers=self.m1_stack,
|
||||||
|
|
|
||||||
|
|
@ -20,15 +20,6 @@ class hierarchical_decoder_test(openram_test):
|
||||||
def runTest(self):
|
def runTest(self):
|
||||||
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
|
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
|
||||||
globals.init_openram(config_file)
|
globals.init_openram(config_file)
|
||||||
# Doesn't require hierarchical decoder
|
|
||||||
# debug.info(1, "Testing 4 row sample for hierarchical_decoder")
|
|
||||||
# a = hierarchical_decoder.hierarchical_decoder(name="hd1, num_outputs=4)
|
|
||||||
# self.local_check(a)
|
|
||||||
|
|
||||||
# Doesn't require hierarchical decoder
|
|
||||||
# debug.info(1, "Testing 8 row sample for hierarchical_decoder")
|
|
||||||
# a = hierarchical_decoder.hierarchical_decoder(name="hd2", num_outputs=8)
|
|
||||||
# self.local_check(a)
|
|
||||||
|
|
||||||
# check hierarchical decoder for single port
|
# check hierarchical decoder for single port
|
||||||
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
|
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue