mirror of https://github.com/VLSIDA/OpenRAM.git
620 lines
26 KiB
Python
620 lines
26 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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import math
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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from errors import drc_error
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from tech import cell_properties
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class hierarchical_decoder(design.design):
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"""
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Dynamically generated hierarchical decoder.
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"""
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def __init__(self, name, num_outputs):
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design.design.__init__(self, name)
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self.AND_FORMAT = "DEC_AND_{0}"
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self.pre2x4_inst = []
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self.pre3x8_inst = []
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b = factory.create(module_type="bitcell")
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try:
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self.cell_multiple = cell_properties.bitcell.decoder_bitcell_multiple
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except AttributeError:
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self.cell_multiple = 1
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# For debugging
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# self.cell_multiple = 2
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self.cell_height = self.cell_multiple * b.height
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self.num_outputs = num_outputs
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self.num_inputs = math.ceil(math.log(self.num_outputs, 2))
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(self.no_of_pre2x4, self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def find_decoder_height(self):
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"""
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Dead code. This would dynamically determine the bitcell multiple,
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but I just decided to hard code it in the tech file if it is not 1
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because a DRC tool would be required even to run in front-end mode.
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"""
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b = factory.create(module_type="bitcell")
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# Old behavior
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if OPTS.netlist_only:
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return (b.height, 1)
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# Search for the smallest multiple that works
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cell_multiple = 1
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while cell_multiple < 5:
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cell_height = cell_multiple * b.height
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# debug.info(2,"Trying mult = {0} height={1}".format(cell_multiple, cell_height))
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try:
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and3 = factory.create(module_type="pand3",
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height=cell_height)
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except drc_error:
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# debug.info(1, "Incrementing decoder height by 1 bitcell height {}".format(b.height))
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pass
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else:
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(drc_errors, lvs_errors) = and3.DRC_LVS(force_check=True)
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total_errors = drc_errors + lvs_errors
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if total_errors == 0:
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debug.info(1, "Decoder height is multiple of {} bitcells.".format(cell_multiple))
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return (cell_height, cell_multiple)
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cell_multiple += 1
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else:
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debug.error("Couldn't find a valid decoder height multiple.", -1)
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def create_netlist(self):
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self.add_modules()
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self.setup_netlist_constants()
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self.add_pins()
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self.create_pre_decoder()
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self.create_row_decoder()
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def create_layout(self):
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self.setup_layout_constants()
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self.place_pre_decoder()
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self.place_row_decoder()
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self.route_inputs()
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self.route_decoder_bus()
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self.route_vdd_gnd()
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self.offset_all_coordinates()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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self.inv = factory.create(module_type="pinv",
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height=self.cell_height)
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self.add_mod(self.inv)
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self.and2 = factory.create(module_type="pand2",
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height=self.cell_height)
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self.add_mod(self.and2)
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self.and3 = factory.create(module_type="pand3",
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height=self.cell_height)
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self.add_mod(self.and3)
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self.add_decoders()
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def add_decoders(self):
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""" Create the decoders based on the number of pre-decodes """
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self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4",
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height=self.cell_height)
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self.add_mod(self.pre2_4)
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self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8",
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height=self.cell_height)
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self.add_mod(self.pre3_8)
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def determine_predecodes(self, num_inputs):
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""" Determines the number of 2:4 pre-decoder and 3:8 pre-decoder
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needed based on the number of inputs """
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if (num_inputs == 2):
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return (1, 0)
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elif (num_inputs == 3):
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return(0, 1)
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elif (num_inputs == 4):
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return(2, 0)
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elif (num_inputs == 5):
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return(1, 1)
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elif (num_inputs == 6):
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return(3, 0)
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elif (num_inputs == 7):
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return(2, 1)
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elif (num_inputs == 8):
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return(1, 2)
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elif (num_inputs == 9):
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return(0, 3)
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else:
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debug.error("Invalid number of inputs for hierarchical decoder", -1)
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def setup_netlist_constants(self):
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self.predec_groups = [] # This array is a 2D array.
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# Distributing vertical bus to different groups. One group belongs to one pre-decoder.
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# For example, for two 2:4 pre-decoder and one 3:8 pre-decoder, we will
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# have total 16 output lines out of these 3 pre-decoders and they will
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# be distributed as [ [0,1,2,3] ,[4,5,6,7], [8,9,10,11,12,13,14,15] ]
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# in self.predec_groups
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index = 0
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for i in range(self.no_of_pre2x4):
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lines = []
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for j in range(4):
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lines.append(index)
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index = index + 1
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self.predec_groups.append(lines)
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for i in range(self.no_of_pre3x8):
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lines = []
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for j in range(8):
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lines.append(index)
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index = index + 1
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self.predec_groups.append(lines)
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def setup_layout_constants(self):
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""" Calculate the overall dimensions of the hierarchical decoder """
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# If we have 4 or fewer rows, the predecoder is the decoder itself
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if self.num_inputs>=4:
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self.total_number_of_predecoder_outputs = 4 * self.no_of_pre2x4 + 8 * self.no_of_pre3x8
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else:
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self.total_number_of_predecoder_outputs = 0
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debug.error("Not enough rows ({}) for a hierarchical decoder. Non-hierarchical not supported yet.".format(self.num_inputs),
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-1)
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# Calculates height and width of pre-decoder,
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if self.no_of_pre3x8 > 0:
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self.predecoder_width = self.pre3_8.width
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else:
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self.predecoder_width = self.pre2_4.width
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self.predecoder_height = self.pre2_4.height * self.no_of_pre2x4 + self.pre3_8.height * self.no_of_pre3x8
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# We may have more than one bitcell per decoder row
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self.num_rows = math.ceil(self.num_outputs / self.cell_multiple)
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# We will place this many final decoders per row
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self.decoders_per_row = math.ceil(self.num_outputs / self.num_rows)
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# Calculates height and width of row-decoder
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if (self.num_inputs == 4 or self.num_inputs == 5):
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nand_width = self.and2.width
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else:
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nand_width = self.and3.width
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self.internal_routing_width = self.m2_pitch * (self.total_number_of_predecoder_outputs + 1)
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self.row_decoder_height = self.inv.height * self.num_rows
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self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch
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# Calculates height and width of hierarchical decoder
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self.height = max(self.predecoder_height, self.row_decoder_height)
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self.width = self.input_routing_width + self.predecoder_width \
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+ self.internal_routing_width \
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+ self.decoders_per_row * nand_width + self.inv.width
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def route_inputs(self):
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""" Create input bus for the predecoders """
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# inputs should be as high as the decoders
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input_height = self.no_of_pre2x4 * self.pre2_4.height + self.no_of_pre3x8 * self.pre3_8.height
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# Find the left-most predecoder
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min_x = 0
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if self.no_of_pre2x4 > 0:
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min_x = min(min_x, self.pre2x4_inst[0].lx())
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if self.no_of_pre3x8 > 0:
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min_x = min(min_x, self.pre3x8_inst[0].lx())
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input_offset=vector(min_x - self.input_routing_width, 0)
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input_bus_names = ["addr_{0}".format(i) for i in range(self.num_inputs)]
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self.input_bus = self.create_vertical_pin_bus(layer="m2",
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pitch=self.m2_pitch,
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offset=input_offset,
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names=input_bus_names,
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length=input_height)
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self.route_input_to_predecodes()
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def route_input_to_predecodes(self):
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""" Route the vertical input rail to the predecoders """
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for pre_num in range(self.no_of_pre2x4):
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for i in range(2):
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index = pre_num * 2 + i
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input_pos = self.input_bus["addr_{}".format(index)]
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in_name = "in_{}".format(i)
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decoder_pin = self.pre2x4_inst[pre_num].get_pin(in_name)
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# To prevent conflicts, we will offset each input connect so
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# that it aligns with the vdd/gnd rails
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decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height)
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input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1)
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self.route_input_bus(decoder_offset, input_offset)
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for pre_num in range(self.no_of_pre3x8):
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for i in range(3):
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index = pre_num * 3 + i + self.no_of_pre2x4 * 2
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input_pos = self.input_bus["addr_{}".format(index)]
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in_name = "in_{}".format(i)
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decoder_pin = self.pre3x8_inst[pre_num].get_pin(in_name)
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# To prevent conflicts, we will offset each input connect so
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# that it aligns with the vdd/gnd rails
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decoder_offset = decoder_pin.bc() + vector(0, (i + 1) * self.inv.height)
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input_offset = input_pos.scale(1, 0) + decoder_offset.scale(0, 1)
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self.route_input_bus(decoder_offset, input_offset)
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def route_input_bus(self, input_offset, output_offset):
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""" Route a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """
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self.add_via_center(layers=self.m2_stack,
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offset=input_offset)
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self.add_via_center(layers=self.m2_stack,
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offset=output_offset)
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self.add_path(("m3"), [input_offset, output_offset])
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def add_pins(self):
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""" Add the module pins """
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for i in range(self.num_inputs):
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self.add_pin("addr_{0}".format(i), "INPUT")
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for j in range(self.num_outputs):
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self.add_pin("decode_{0}".format(j), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_pre_decoder(self):
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""" Creates pre-decoder and places labels input address [A] """
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for i in range(self.no_of_pre2x4):
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self.create_pre2x4(i)
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for i in range(self.no_of_pre3x8):
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self.create_pre3x8(i)
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def create_pre2x4(self, num):
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""" Add a 2x4 predecoder to the left of the origin """
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if (self.num_inputs == 2):
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index_off1 = index_off2 = 0
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else:
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index_off1 = num * 2
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index_off2 = num * 4
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pins = []
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for input_index in range(2):
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pins.append("addr_{0}".format(input_index + index_off1))
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for output_index in range(4):
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pins.append("out_{0}".format(output_index + index_off2))
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pins.extend(["vdd", "gnd"])
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self.pre2x4_inst.append(self.add_inst(name="pre_{0}".format(num),
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mod=self.pre2_4))
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self.connect_inst(pins)
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def create_pre3x8(self, num):
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""" Add 3x8 predecoder to the left of the origin and above any 2x4 decoders """
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# If we had 2x4 predecodes, those are used as the lower
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# decode output bits
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in_index_offset = num * 3 + self.no_of_pre2x4 * 2
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out_index_offset = num * 8 + self.no_of_pre2x4 * 4
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pins = []
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for input_index in range(3):
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pins.append("addr_{0}".format(input_index + in_index_offset))
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for output_index in range(8):
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pins.append("out_{0}".format(output_index + out_index_offset))
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pins.extend(["vdd", "gnd"])
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self.pre3x8_inst.append(self.add_inst(name="pre3x8_{0}".format(num),
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mod=self.pre3_8))
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self.connect_inst(pins)
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def place_pre_decoder(self):
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""" Creates pre-decoder and places labels input address [A] """
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for i in range(self.no_of_pre2x4):
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self.place_pre2x4(i)
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for i in range(self.no_of_pre3x8):
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self.place_pre3x8(i)
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def place_pre2x4(self, num):
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""" Place 2x4 predecoder to the left of the origin """
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if (self.num_inputs == 2):
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base = vector(-self.pre2_4.width, 0)
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else:
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base= vector(-self.pre2_4.width, num * self.pre2_4.height)
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self.pre2x4_inst[num].place(base - vector(2 * self.m2_pitch, 0))
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def place_pre3x8(self, num):
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""" Place 3x8 predecoder to the left of the origin and above any 2x4 decoders """
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if (self.num_inputs == 3):
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offset = vector(-self.pre_3_8.width, 0)
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else:
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height = self.no_of_pre2x4 * self.pre2_4.height + num * self.pre3_8.height
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offset = vector(-self.pre3_8.width, height)
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self.pre3x8_inst[num].place(offset - vector(2 * self.m2_pitch, 0))
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def create_row_decoder(self):
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""" Create the row-decoder by placing AND2/AND3 and Inverters
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and add the primary decoder output pins. """
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if (self.num_inputs >= 4):
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self.create_decoder_and_array()
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def create_decoder_and_array(self):
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""" Add a column of AND gates for final decode """
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self.and_inst = []
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# Row Decoder AND GATE array for address inputs <5.
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if (self.num_inputs == 4 or self.num_inputs == 5):
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for i in range(len(self.predec_groups[0])):
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for j in range(len(self.predec_groups[1])):
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output = len(self.predec_groups[0]) * j + i
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if (output < self.num_outputs):
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name = self.AND_FORMAT.format(output)
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self.and_inst.append(self.add_inst(name=name,
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mod=self.and2))
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pins =["out_{0}".format(i),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"decode_{0}".format(output),
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"vdd", "gnd"]
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self.connect_inst(pins)
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# Row Decoder AND GATE array for address inputs >5.
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elif (self.num_inputs > 5):
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for i in range(len(self.predec_groups[0])):
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for j in range(len(self.predec_groups[1])):
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for k in range(len(self.predec_groups[2])):
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output = (len(self.predec_groups[0]) * len(self.predec_groups[1])) * k \
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+ len(self.predec_groups[0]) * j + i
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if (output < self.num_outputs):
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name = self.AND_FORMAT.format(output)
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self.and_inst.append(self.add_inst(name=name,
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mod=self.and3))
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pins = ["out_{0}".format(i),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"out_{0}".format(k + len(self.predec_groups[0]) + len(self.predec_groups[1])),
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"decode_{0}".format(output),
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"vdd", "gnd"]
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self.connect_inst(pins)
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def place_row_decoder(self):
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"""
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Place the row-decoder by placing AND2/AND3 and Inverters
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and add the primary decoder output pins.
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"""
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if (self.num_inputs >= 4):
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self.place_decoder_and_array()
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self.route_decoder()
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def place_decoder_and_array(self):
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"""
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Add a column of AND gates for final decode.
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This may have more than one decoder per row to match the bitcell height.
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"""
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# Row Decoder AND GATE array for address inputs <5.
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if (self.num_inputs == 4 or self.num_inputs == 5):
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self.place_and_array(and_mod=self.and2)
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# Row Decoder AND GATE array for address inputs >5.
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# FIXME: why this correct offset?)
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elif (self.num_inputs > 5):
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self.place_and_array(and_mod=self.and3)
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def place_and_array(self, and_mod):
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"""
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Add a column of AND gates for the decoder above the predecoders.
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"""
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for inst_index in range(self.num_outputs):
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row = math.floor(inst_index / self.decoders_per_row)
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dec = inst_index % self.decoders_per_row
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if ((row % 2) == 0):
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y_off = and_mod.height * row
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mirror = "R0"
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else:
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y_off = and_mod.height * (row + 1)
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mirror = "MX"
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x_off = self.internal_routing_width + dec * and_mod.width
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self.and_inst[inst_index].place(offset=vector(x_off, y_off),
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mirror=mirror)
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def route_decoder(self):
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""" Add the pins. """
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for output in range(self.num_outputs):
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z_pin = self.and_inst[output].get_pin("Z")
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self.add_layout_pin(text="decode_{0}".format(output),
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layer="m1",
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offset=z_pin.ll(),
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width=z_pin.width(),
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height=z_pin.height())
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def route_decoder_bus(self):
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"""
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Creates vertical metal 2 bus to connect predecoder and decoder stages.
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"""
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# This is not needed for inputs <4 since they have no pre/decode stages.
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if (self.num_inputs >= 4):
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# This leaves an offset for the predecoder output jogs
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input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)]
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self.predecode_bus = self.create_vertical_pin_bus(layer="m2",
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pitch=self.m2_pitch,
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offset=vector(0, 0),
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names=input_bus_names,
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length=self.height)
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self.route_bus_to_predecodes()
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self.route_bus_to_decoder()
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def route_bus_to_predecodes(self):
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"""
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Iterates through all of the predecodes
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and connects to the rails including the offsets
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"""
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# FIXME: convert to connect_bus
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for pre_num in range(self.no_of_pre2x4):
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for i in range(4):
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predecode_name = "predecode_{}".format(pre_num * 4 + i)
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out_name = "out_{}".format(i)
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pin = self.pre2x4_inst[pre_num].get_pin(out_name)
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x_offset = self.pre2x4_inst[pre_num].rx() + self.m2_pitch
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self.route_predecode_bus_inputs(predecode_name, pin, x_offset)
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# FIXME: convert to connect_bus
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for pre_num in range(self.no_of_pre3x8):
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for i in range(8):
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predecode_name = "predecode_{}".format(pre_num * 8 + i + self.no_of_pre2x4 * 4)
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out_name = "out_{}".format(i)
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pin = self.pre3x8_inst[pre_num].get_pin(out_name)
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x_offset = self.pre3x8_inst[pre_num].rx() + self.m2_pitch
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self.route_predecode_bus_inputs(predecode_name, pin, x_offset)
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def route_bus_to_decoder(self):
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"""
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Use the self.predec_groups to determine the connections to the decoder AND gates.
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|
Inputs of AND2/AND3 gates come from different groups.
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For example for these groups
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[ [0,1,2,3] ,[4,5,6,7], [8,9,10,11,12,13,14,15] ]
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the first AND3 inputs are connected to [0,4,8],
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second AND3 is connected to [0,4,9],
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...
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and the 128th AND3 is connected to [3,7,15]
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"""
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output_index = 0
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|
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if (self.num_inputs == 4 or self.num_inputs == 5):
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for index_B in self.predec_groups[1]:
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for index_A in self.predec_groups[0]:
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# FIXME: convert to connect_bus?
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if (output_index < self.num_outputs):
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row_index = math.floor(output_index / self.decoders_per_row)
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row_remainder = (output_index % self.decoders_per_row)
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row_offset = row_index * self.and_inst[0].height + (2 * row_remainder + 4) * self.m1_pitch
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_bus_outputs(predecode_name,
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self.and_inst[output_index].get_pin("A"),
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row_offset)
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predecode_name = "predecode_{}".format(index_B)
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self.route_predecode_bus_outputs(predecode_name,
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self.and_inst[output_index].get_pin("B"),
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row_offset + self.m1_pitch)
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output_index = output_index + 1
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|
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elif (self.num_inputs > 5):
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for index_C in self.predec_groups[2]:
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for index_B in self.predec_groups[1]:
|
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for index_A in self.predec_groups[0]:
|
|
# FIXME: convert to connect_bus?
|
|
if (output_index < self.num_outputs):
|
|
row_index = math.floor(output_index / self.decoders_per_row)
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|
row_remainder = (output_index % self.decoders_per_row)
|
|
row_offset = row_index * self.and_inst[0].height + (3 * row_remainder + 4) * self.m1_pitch
|
|
predecode_name = "predecode_{}".format(index_A)
|
|
self.route_predecode_bus_outputs(predecode_name,
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|
self.and_inst[output_index].get_pin("A"),
|
|
row_offset)
|
|
predecode_name = "predecode_{}".format(index_B)
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|
self.route_predecode_bus_outputs(predecode_name,
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|
self.and_inst[output_index].get_pin("B"),
|
|
row_offset + self.m1_pitch)
|
|
predecode_name = "predecode_{}".format(index_C)
|
|
self.route_predecode_bus_outputs(predecode_name,
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|
self.and_inst[output_index].get_pin("C"),
|
|
row_offset + 2 * self.m1_pitch)
|
|
output_index = output_index + 1
|
|
|
|
def route_vdd_gnd(self):
|
|
"""
|
|
Add a pin for each row of vdd/gnd which are
|
|
must-connects next level up.
|
|
"""
|
|
|
|
# The vias will be placed in the center and right of the cells, respectively.
|
|
xoffset = self.and_inst[0].rx()
|
|
for num in range(0, self.num_outputs):
|
|
for pin_name in ["vdd", "gnd"]:
|
|
# The nand and inv are the same height rows...
|
|
supply_pin = self.and_inst[num].get_pin(pin_name)
|
|
pin_pos = vector(xoffset, supply_pin.cy())
|
|
self.add_power_pin(name=pin_name,
|
|
loc=pin_pos)
|
|
|
|
# Copy the pins from the predecoders
|
|
for pre in self.pre2x4_inst + self.pre3x8_inst:
|
|
self.copy_layout_pin(pre, "vdd")
|
|
self.copy_layout_pin(pre, "gnd")
|
|
|
|
def route_predecode_bus_outputs(self, rail_name, pin, y_offset):
|
|
"""
|
|
Connect the routing rail to the given metal1 pin
|
|
using a routing track at the given y_offset
|
|
|
|
"""
|
|
pin_pos = pin.center()
|
|
# If we have a single decoder per row, we can route on M1
|
|
if self.decoders_per_row == 1:
|
|
rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y)
|
|
self.add_path("m1", [rail_pos, pin_pos])
|
|
self.add_via_center(layers=self.m1_stack,
|
|
offset=rail_pos)
|
|
# If not, we must route over the decoder cells on M3
|
|
else:
|
|
rail_pos = vector(self.predecode_bus[rail_name].x, y_offset)
|
|
mid_pos = vector(pin_pos.x, rail_pos.y)
|
|
self.add_wire(self.m2_stack[::-1], [rail_pos, mid_pos, pin_pos])
|
|
self.add_via_center(layers=self.m2_stack,
|
|
offset=rail_pos)
|
|
self.add_via_center(layers=self.m1_stack,
|
|
offset=pin_pos)
|
|
|
|
def route_predecode_bus_inputs(self, rail_name, pin, x_offset):
|
|
"""
|
|
Connect the routing rail to the given metal1 pin using a jog
|
|
to the right of the cell at the given x_offset.
|
|
"""
|
|
# This routes the pin up to the rail, basically, to avoid conflicts.
|
|
# It would be fixed with a channel router.
|
|
pin_pos = pin.center()
|
|
mid_point1 = vector(x_offset, pin_pos.y)
|
|
mid_point2 = vector(x_offset, pin_pos.y + self.inv.height / 2)
|
|
rail_pos = vector(self.predecode_bus[rail_name].x, mid_point2.y)
|
|
self.add_wire(self.m1_stack, [pin_pos, mid_point1, mid_point2, rail_pos])
|
|
self.add_via_center(layers=self.m1_stack,
|
|
offset=rail_pos)
|
|
|
|
def input_load(self):
|
|
if self.determine_predecodes(self.num_inputs)[1]==0:
|
|
pre = self.pre2_4
|
|
else:
|
|
pre = self.pre3_8
|
|
return pre.input_load()
|
|
|