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revert changes to pinvbuf

This commit is contained in:
Jacob Walker 2023-03-02 22:47:47 -08:00
parent 382c91f342
commit 2d5199961d
2 changed files with 9 additions and 28 deletions
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36
compiler/modules/pinvbuf.py
View File

@ -17,14 +17,13 @@ class pinvbuf(pgate):
This is a simple inverter/buffer used for driving loads. It is This is a simple inverter/buffer used for driving loads. It is
used in the column decoder for 1:2 decoding and as the clock buffer. used in the column decoder for 1:2 decoding and as the clock buffer.
""" """
def __init__(self, name, size=4, height=None, route_in_cell=False): def __init__(self, name, size=4, height=None):
debug.info(1, "creating pinvbuf {}".format(name)) debug.info(1, "creating pinvbuf {}".format(name))
self.add_comment("size: {}".format(size)) self.add_comment("size: {}".format(size))
self.stage_effort = 4 self.stage_effort = 4
self.row_height = height self.row_height = height
self.route_in_cell = route_in_cell
# FIXME: Change the number of stages to support high drives. # FIXME: Change the number of stages to support high drives.
# stage effort of 4 or less # stage effort of 4 or less
@ -135,33 +134,14 @@ class pinvbuf(pgate):
z1_pin = self.inv1_inst.get_pin("Z") z1_pin = self.inv1_inst.get_pin("Z")
a4_pin = self.inv4_inst.get_pin("A") a4_pin = self.inv4_inst.get_pin("A")
if self.route_in_cell:
# inv1 Z to inv4 A (under and up)
mid_point = vector(a4_pin.cx(), z1_pin.cy())
end_point = a4_pin.center()
# end_point = vector(a4_pin.cx(), a4_pin.by() - self.m1_space - self.contact_space)
self.add_path(route_stack[2],
[z1_pin.center(), mid_point, end_point])
self.add_via_stack_center(from_layer=z1_pin.layer, # inv1 Z to inv4 A (up and over)
to_layer=route_stack[2], mid_point = vector(z1_pin.cx(), a4_pin.cy())
offset=z1_pin.center()) self.add_wire(route_stack,
[z1_pin.center(), mid_point, a4_pin.center()])
self.add_via_stack_center(from_layer=a4_pin.layer, self.add_via_stack_center(from_layer=z1_pin.layer,
to_layer=route_stack[2], to_layer=route_stack[2],
offset=end_point) offset=z1_pin.center())
self.add_segment_center(a4_pin.layer, end_point, a4_pin.center())
else:
# inv1 Z to inv4 A (up and over)
mid_point = vector(z1_pin.cx(), a4_pin.cy())
self.add_wire(route_stack,
[z1_pin.center(), mid_point, a4_pin.center()])
self.add_via_stack_center(from_layer=z1_pin.layer,
to_layer=route_stack[2],
offset=z1_pin.center())
def add_layout_pins(self): def add_layout_pins(self):

1
compiler/modules/rom_control_logic.py
View File

@ -90,6 +90,7 @@ class rom_control_logic(design):
self.nand_inst.place(offset=[self.buf_inst.width, 0]) self.nand_inst.place(offset=[self.buf_inst.width, 0])
self.driver_inst.place(offset=[0, self.buf_inst.height + self.driver_inst.height], mirror="MX") self.driver_inst.place(offset=[0, self.buf_inst.height + self.driver_inst.height], mirror="MX")
# hack to get around the fact these modules dont tile properly
offset = self.driver_inst.get_pin("vdd").cy() - self.nand_inst.get_pin("vdd").cy() offset = self.driver_inst.get_pin("vdd").cy() - self.nand_inst.get_pin("vdd").cy()
self.driver_inst.place(offset=[0, self.buf_inst.height + self.driver_inst.height - offset], mirror="MX") self.driver_inst.place(offset=[0, self.buf_inst.height + self.driver_inst.height - offset], mirror="MX")