diff --git a/compiler/modules/pinvbuf.py b/compiler/modules/pinvbuf.py
index c71c6da9..f05a2e5b 100644
--- a/compiler/modules/pinvbuf.py
+++ b/compiler/modules/pinvbuf.py
@@ -17,14 +17,13 @@ class pinvbuf(pgate):
     This is a simple inverter/buffer used for driving loads. It is
     used in the column decoder for 1:2 decoding and as the clock buffer.
     """
-    def __init__(self, name, size=4, height=None, route_in_cell=False):
+    def __init__(self, name, size=4, height=None):
 
         debug.info(1, "creating pinvbuf {}".format(name))
         self.add_comment("size: {}".format(size))
 
         self.stage_effort = 4
         self.row_height = height
-        self.route_in_cell = route_in_cell
         # FIXME: Change the number of stages to support high drives.
 
         # stage effort of 4 or less
@@ -135,33 +134,14 @@ class pinvbuf(pgate):
 
         z1_pin = self.inv1_inst.get_pin("Z")
         a4_pin = self.inv4_inst.get_pin("A")
-        if self.route_in_cell:
-            # inv1 Z to inv4 A (under and up)
-            mid_point = vector(a4_pin.cx(), z1_pin.cy())
-            end_point = a4_pin.center()
-            # end_point = vector(a4_pin.cx(), a4_pin.by() - self.m1_space - self.contact_space)
-            self.add_path(route_stack[2],
-                        [z1_pin.center(), mid_point, end_point])
 
-            self.add_via_stack_center(from_layer=z1_pin.layer,
-                                    to_layer=route_stack[2],
-                                    offset=z1_pin.center())
-
-            self.add_via_stack_center(from_layer=a4_pin.layer,
-                                    to_layer=route_stack[2],
-                                    offset=end_point)
-
-
-            self.add_segment_center(a4_pin.layer, end_point, a4_pin.center())
-        else:
-            # inv1 Z to inv4 A (up and over)
-
-            mid_point = vector(z1_pin.cx(), a4_pin.cy())
-            self.add_wire(route_stack,
-                        [z1_pin.center(), mid_point, a4_pin.center()])
-            self.add_via_stack_center(from_layer=z1_pin.layer,
-                                    to_layer=route_stack[2],
-                                    offset=z1_pin.center())
+        # inv1 Z to inv4 A (up and over)
+        mid_point = vector(z1_pin.cx(), a4_pin.cy())
+        self.add_wire(route_stack,
+                    [z1_pin.center(), mid_point, a4_pin.center()])
+        self.add_via_stack_center(from_layer=z1_pin.layer,
+                                to_layer=route_stack[2],
+                                offset=z1_pin.center())
 
     def add_layout_pins(self):
 
diff --git a/compiler/modules/rom_control_logic.py b/compiler/modules/rom_control_logic.py
index af8b81a0..a6dca49d 100644
--- a/compiler/modules/rom_control_logic.py
+++ b/compiler/modules/rom_control_logic.py
@@ -90,6 +90,7 @@ class rom_control_logic(design):
         self.nand_inst.place(offset=[self.buf_inst.width, 0])
         self.driver_inst.place(offset=[0, self.buf_inst.height + self.driver_inst.height], mirror="MX")
 
+        # hack to get around the fact these modules dont tile properly
         offset = self.driver_inst.get_pin("vdd").cy() - self.nand_inst.get_pin("vdd").cy()
         self.driver_inst.place(offset=[0, self.buf_inst.height + self.driver_inst.height - offset], mirror="MX")