From 2c9f755a73b6d9827069f6792773e1aebd7ab7f6 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 12 Jul 2021 14:25:37 -0700 Subject: [PATCH] Added on resistance functions for pgates, custom cells, and bitcell. --- compiler/base/hierarchy_spice.py | 4 ++-- compiler/bitcells/bitcell_base.py | 6 ++++++ compiler/custom/nand2_dec.py | 7 +++++++ compiler/custom/nand3_dec.py | 7 +++++++ compiler/custom/nand4_dec.py | 7 +++++++ compiler/custom/sense_amp.py | 7 +++++++ compiler/pgates/pinv.py | 7 +++++++ compiler/pgates/pnand2.py | 10 +++++++++- compiler/pgates/pnand3.py | 9 ++++++++- compiler/pgates/pnand4.py | 7 +++++++ compiler/pgates/ptx.py | 7 +++++++ 11 files changed, 74 insertions(+), 4 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 75970a15..93e34dbf 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -515,7 +515,7 @@ class spice(): return td - def tr_r_on(width, nchannel, stack, _is_cell): + def tr_r_on(width, is_nchannel, stack, _is_cell): # FIXME: temp code until parameters have been determined if _is_cell: @@ -524,7 +524,7 @@ class spice(): dt = tech.peri_global - restrans = dt.R_nch_on if nchannel else dt.R_pch_on + restrans = dt.R_nch_on if is_nchannel else dt.R_pch_on return stack * restrans / width def gate_c(width, wirelength, _is_cell) diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 1161fec8..2b27bee9 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -202,3 +202,9 @@ class bitcell_base(design.design): debug.check(port == 0, "One port for bitcell only.") return "wl" + def get_on_resistance(self): + """On resistance of pinv, defined by single nmos""" + is_nchannel = True + stack = 2 # for access and inv tx + is_cell = False + return self.tr_r_on(drc["minwidth_tx"], is_nchannel, stack, is_cell) \ No newline at end of file diff --git a/compiler/custom/nand2_dec.py b/compiler/custom/nand2_dec.py index 893bb34f..a1418062 100644 --- a/compiler/custom/nand2_dec.py +++ b/compiler/custom/nand2_dec.py @@ -74,3 +74,10 @@ class nand2_dec(design.design): """Return input to output polarity for module""" return False + + def get_on_resistance(self): + """On resistance of pnand, defined by stacked NMOS""" + is_nchannel = True + stack = 2 + is_cell = False + return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell) diff --git a/compiler/custom/nand3_dec.py b/compiler/custom/nand3_dec.py index a887e38f..da745bd2 100644 --- a/compiler/custom/nand3_dec.py +++ b/compiler/custom/nand3_dec.py @@ -74,3 +74,10 @@ class nand3_dec(design.design): """Return input to output polarity for module""" return False + + def get_on_resistance(self): + """On resistance of pnand, defined by stacked NMOS""" + is_nchannel = True + stack = 3 + is_cell = False + return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell) \ No newline at end of file diff --git a/compiler/custom/nand4_dec.py b/compiler/custom/nand4_dec.py index d3b6491d..1ddefed4 100644 --- a/compiler/custom/nand4_dec.py +++ b/compiler/custom/nand4_dec.py @@ -74,3 +74,10 @@ class nand4_dec(design.design): """Return input to output polarity for module""" return False + + def get_on_resistance(self): + """On resistance of pnand, defined by stacked NMOS""" + is_nchannel = True + stack = 4 + is_cell = False + return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell) \ No newline at end of file diff --git a/compiler/custom/sense_amp.py b/compiler/custom/sense_amp.py index d3268713..8446756d 100644 --- a/compiler/custom/sense_amp.py +++ b/compiler/custom/sense_amp.py @@ -79,3 +79,10 @@ class sense_amp(design.design): #FIXME: This only applied to bl/br -> dout and not s_en->dout return True + + def get_on_resistance(self): + """On resistance of pinv, defined by single nmos""" + is_nchannel = False + stack = 1 + is_cell = False + return self.tr_r_on(parameter["sa_inv_nmos_size"], is_nchannel, stack, is_cell) diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index e4aecca5..0d464ee6 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -342,3 +342,10 @@ class pinv(pgate.pgate): """Return input to output polarity for module""" return False + + def get_on_resistance(self): + """On resistance of pinv, defined by single nmos""" + is_nchannel = True + stack = 1 + is_cell = False + return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index f2a579e8..e5619b1f 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -318,4 +318,12 @@ class pnand2(pgate.pgate): def is_non_inverting(self): """Return input to output polarity for module""" - return False \ No newline at end of file + return False + + def get_on_resistance(self): + """On resistance of pnand, defined by stacked NMOS""" + is_nchannel = True + stack = 2 + is_cell = False + return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell) + \ No newline at end of file diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 1c14092b..acc20ec5 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -351,4 +351,11 @@ class pnand3(pgate.pgate): def is_non_inverting(self): """Return input to output polarity for module""" - return False \ No newline at end of file + return False + + def get_on_resistance(self): + """On resistance of pnand, defined by stacked NMOS""" + is_nchannel = True + stack = 3 + is_cell = False + return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell) \ No newline at end of file diff --git a/compiler/pgates/pnand4.py b/compiler/pgates/pnand4.py index 2a88f2d1..eec42916 100644 --- a/compiler/pgates/pnand4.py +++ b/compiler/pgates/pnand4.py @@ -369,3 +369,10 @@ class pnand4(pgate.pgate): Overrides base class function. """ self.add_graph_edges(graph, port_nets) + + def get_on_resistance(self): + """On resistance of pnand, defined by stacked NMOS""" + is_nchannel = True + stack = 4 + is_cell = False + return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index a2928ce1..9bdf82a6 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -552,3 +552,10 @@ class ptx(design.design): """Return input to output polarity for module""" return True + + def get_on_resistance(self): + """On resistance of pinv, defined by single nmos""" + is_nchannel = True + stack = 1 + is_cell = False + return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell) \ No newline at end of file