mirror of https://github.com/VLSIDA/OpenRAM.git
uncomment function sim and datasheet generation
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parent
25bc178132
commit
2b9df2ff1f
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@ -84,9 +84,9 @@ class sram():
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debug.print_raw("SP: Writing to {0}".format(spname))
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debug.print_raw("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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self.sp_write(spname)
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functional(self.s,
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functional(self.s,
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os.path.basename(spname),
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os.path.basename(spname),
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cycles=200,
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cycles=200,
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output_path=OPTS.output_path)
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output_path=OPTS.output_path)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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if not OPTS.netlist_only:
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if not OPTS.netlist_only:
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@ -142,7 +142,7 @@ class sram():
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start_time = datetime.datetime.now()
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start_time = datetime.datetime.now()
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from characterizer import lib
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from characterizer import lib
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debug.print_raw("LIB: Characterizing... ")
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debug.print_raw("LIB: Characterizing... ")
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lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
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lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
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print_time("Characterization", datetime.datetime.now(), start_time)
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print_time("Characterization", datetime.datetime.now(), start_time)
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# Write the config file
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# Write the config file
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@ -157,7 +157,7 @@ class sram():
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from datasheet_gen import datasheet_gen
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from datasheet_gen import datasheet_gen
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dname = OPTS.output_path + self.s.name + ".html"
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dname = OPTS.output_path + self.s.name + ".html"
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debug.print_raw("Datasheet: Writing to {0}".format(dname))
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debug.print_raw("Datasheet: Writing to {0}".format(dname))
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datasheet_gen.datasheet_write(dname)
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datasheet_gen.datasheet_write(dname)
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print_time("Datasheet", datetime.datetime.now(), start_time)
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print_time("Datasheet", datetime.datetime.now(), start_time)
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# Write a verilog model
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# Write a verilog model
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