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Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins.

This commit is contained in:
Matt Guthaus 2018-02-27 08:59:46 -08:00
parent 01244347c1
commit 2b839d34a3
3 changed files with 12 additions and 12 deletions
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4
compiler/base/hierarchy_spice.py
View File

@ -97,8 +97,8 @@ class spice(verilog.verilog):
for i in range(len(self.spice)): for i in range(len(self.spice)):
self.spice[i] = self.spice[i].rstrip(" \n") self.spice[i] = self.spice[i].rstrip(" \n")
# find first subckt line in the file # find the correct subckt line in the file
subckt = re.compile("^.subckt", re.IGNORECASE) subckt = re.compile("^.subckt {}".format(self.name), re.IGNORECASE)
subckt_line = filter(subckt.search, self.spice)[0] subckt_line = filter(subckt.search, self.spice)[0]
# parses line into ports and remove subckt # parses line into ports and remove subckt
self.pins = subckt_line.split(" ")[2:] self.pins = subckt_line.split(" ")[2:]

10
technology/freepdk45/sp_lib/ms_flop.sp vendored
View File

@ -1,10 +1,5 @@
*master-slave flip-flop with both output and inverted ouput *master-slave flip-flop with both output and inverted ouput
.SUBCKT ms_flop din dout dout_bar clk vdd gnd
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
.ENDS flop
.SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd .SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd
*clk inverter *clk inverter
mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1 mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1
@ -27,3 +22,8 @@ mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1
mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1 mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1
.ENDS dlatch .ENDS dlatch
.SUBCKT ms_flop din dout dout_bar clk vdd gnd
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
.ENDS flop

10
technology/scn3me_subm/sp_lib/ms_flop.sp vendored
View File

@ -1,10 +1,5 @@
*master-slave flip-flop with both output and inverted ouput *master-slave flip-flop with both output and inverted ouput
.subckt ms_flop din dout dout_bar clk vdd gnd
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
.ends flop
.subckt dlatch din dout dout_bar clk clk_bar vdd gnd .subckt dlatch din dout dout_bar clk clk_bar vdd gnd
*clk inverter *clk inverter
mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1 mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1
@ -27,3 +22,8 @@ mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1
mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1 mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1
.ends dlatch .ends dlatch
.subckt ms_flop din dout dout_bar clk vdd gnd
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
.ends flop