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Added bitcell as input to array, but there are DRC errors now.

This commit is contained in:
Hunter Nichols 2019-06-17 15:31:16 -07:00
parent 36214792eb
commit 2b07db33c8
5 changed files with 39 additions and 35 deletions
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12
compiler/modules/bank.py
View File

@ -401,18 +401,18 @@ class bank(design.design):
def add_modules(self):
""" Add all the modules using the class loader """
self.bitcell_array = factory.create(module_type="bitcell_array",
cols=self.num_cols,
rows=self.num_rows)
self.add_mod(self.bitcell_array)
# create arrays of bitline and bitline_bar names for read, write, or all ports
self.bitcell = factory.create(module_type="bitcell")
self.bl_names = self.bitcell.list_all_bl_names()
self.br_names = self.bitcell.list_all_br_names()
self.wl_names = self.bitcell.list_all_wl_names()
self.bitline_names = self.bitcell.list_all_bitline_names()
self.bitcell_array = factory.create(module_type="bitcell_array",
cols=self.num_cols,
rows=self.num_rows,
bitcell=self.bitcell)
self.add_mod(self.bitcell_array)
self.precharge_array = []
for port in self.all_ports:

5
compiler/modules/bitcell_array.py
View File

@ -19,13 +19,14 @@ class bitcell_array(design.design):
and word line is connected by abutment.
Connects the word lines and bit lines.
"""
def __init__(self, cols, rows, name):
def __init__(self, cols, rows, name, bitcell):
design.design.__init__(self, name)
debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
self.add_comment("rows: {0} cols: {1}".format(rows, cols))
self.column_size = cols
self.row_size = rows
self.cell = bitcell
self.create_netlist()
if not OPTS.netlist_only:
@ -84,8 +85,6 @@ class bitcell_array(design.design):
def add_modules(self):
""" Add the modules used in this design """
self.cell = factory.create(module_type="bitcell")
debug.info(1,"Cell mod created, id={}".format(id(self.cell)))
self.add_mod(self.cell)
def create_instances(self):

4
compiler/modules/replica_bitline.py
View File

@ -86,10 +86,12 @@ class replica_bitline(design.design):
self.replica_bitcell = factory.create(module_type="replica_bitcell")
self.add_mod(self.replica_bitcell)
bitcell = factory.create(module_type="bitcell")
# This is the replica bitline load column that is the height of our array
self.rbl = factory.create(module_type="bitcell_array",
cols=1,
rows=self.bitcell_loads)
rows=self.bitcell_loads,
bitcell=bitcell)
self.add_mod(self.rbl)
# FIXME: The FO and depth of this should be tuned

2
compiler/sram_factory.py
View File

@ -65,6 +65,8 @@ class sram_factory:
# Must have the same dictionary exactly (conservative)
if obj_kwargs == kwargs:
#debug.info(0, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs)))
if module_type == 'bitcell_array':
debug.info(1,'Returning existing mod!')
return obj_item
#else:
# print("obj",obj_kwargs)

51
compiler/tests/16_control_logic_test.py
View File

@ -26,36 +26,37 @@ class control_logic_test(openram_test):
import control_logic
import tech
# check control logic for single port
debug.info(1, "Testing sample for control_logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
self.local_check(a)
# # check control logic for single port
# debug.info(1, "Testing sample for control_logic")
# a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
# self.local_check(a)
# check control logic for multi-port
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for control_logic for multiport")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8)
self.local_check(a)
# Check port specific control logic
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
self.local_check(a)
#OPTS.num_rw_ports = 1
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w")
self.local_check(a)
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
# debug.info(1, "Testing sample for control_logic for multiport")
# a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8)
# self.local_check(a)
# # Check port specific control logic
# OPTS.num_rw_ports = 1
# OPTS.num_w_ports = 0
# OPTS.num_r_ports = 0
# debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
# a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
# self.local_check(a)
# OPTS.num_rw_ports = 0
# OPTS.num_w_ports = 1
# debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
# a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w")
# self.local_check(a)
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1