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Added bitcell as input to array, but there are DRC errors now.

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Hunter Nichols
2019-06-17 15:31:16 -07:00
parent 36214792eb
commit 2b07db33c8
5 changed files with 39 additions and 35 deletions
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compiler/tests/16_control_logic_test.py
+26 -25
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@@ -26,36 +26,37 @@ class control_logic_test(openram_test):
import control_logic
import tech
# check control logic for single port
debug.info(1, "Testing sample for control_logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
self.local_check(a)
# # check control logic for single port
# debug.info(1, "Testing sample for control_logic")
# a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
# self.local_check(a)
# check control logic for multi-port
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for control_logic for multiport")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8)
self.local_check(a)
# Check port specific control logic
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
self.local_check(a)
#OPTS.num_rw_ports = 1
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w")
self.local_check(a)
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
# debug.info(1, "Testing sample for control_logic for multiport")
# a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8)
# self.local_check(a)
# # Check port specific control logic
# OPTS.num_rw_ports = 1
# OPTS.num_w_ports = 0
# OPTS.num_r_ports = 0
# debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
# a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
# self.local_check(a)
# OPTS.num_rw_ports = 0
# OPTS.num_w_ports = 1
# debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
# a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w")
# self.local_check(a)
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1